source: rtems/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c @ f05b2ac

4.104.114.84.9
Last change on this file since f05b2ac was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 21, 2004 at 4:01:48 PM

Remove duplicate white lines.

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File size: 4.8 KB
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1 /*
2 *  This file contains the table for the z85c30 port
3 *  used by the console driver.
4 *
5 *  COPYRIGHT (c) 1989-1997.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id:
13 */
14
15#include "consolebsp.h"
16#include <bsp.h>
17
18#define CONSOLE_DEFAULT_BAUD_RATE            9600
19#define CONSOLE_DEFAULT_BAUD_CONSTANT        Score603e_Z8530_Chip0_Baud(9600)
20
21#define CONSOLE_DEFAULT_STOP_BITS            CONSOLE_STOP_BITS_1
22#define CONSOLE_DEFAULT_PARITY               CONSOLE_PARITY_NONE
23#define CONSOLE_DEFAULT_READ_CHARACTER_BITS  CONSOLE_CHARACTER_BITS_8
24#define CONSOLE_DEFAULT_WRITE_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8
25#define CONSOLE_DEFAULT_CONSOLE_CLOCK        CONSOLE_x16_CLOCK
26
27#define DEFAULT_PROTOCOL  { CONSOLE_DEFAULT_BAUD_RATE,              \
28                            CONSOLE_DEFAULT_STOP_BITS,              \
29                            CONSOLE_DEFAULT_PARITY,                 \
30                            CONSOLE_DEFAULT_READ_CHARACTER_BITS,    \
31                            CONSOLE_DEFAULT_WRITE_CHARACTER_BITS }
32
33/*
34 * Tables of information necessary to use the console 85c30 routines.
35 */
36Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] =
37{
38  DEFAULT_PROTOCOL,
39  DEFAULT_PROTOCOL,
40  DEFAULT_PROTOCOL,
41  DEFAULT_PROTOCOL,
42
43#if (HAS_PMC_PSC8)
44  DEFAULT_PROTOCOL,
45  DEFAULT_PROTOCOL,
46  DEFAULT_PROTOCOL,
47  DEFAULT_PROTOCOL,
48  DEFAULT_PROTOCOL,
49  DEFAULT_PROTOCOL,
50  DEFAULT_PROTOCOL,
51  DEFAULT_PROTOCOL,
52#endif
53};
54
55/*
56 * Table of chip unique information for each chip.
57 * See consolebsp.h for the Chip_85C30_info structure defination.
58 */
59Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] =
60{
61  {
62    SCORE603E_85C30_0_IRQ,
63    SCORE603E_85C30_0_CLOCK,
64    SCORE603E_85C30_0_CLOCK_X,
65    CONSOLE_DEFAULT_CONSOLE_CLOCK
66  },
67  {
68    SCORE603E_85C30_1_IRQ,
69    SCORE603E_85C30_1_CLOCK,
70    SCORE603E_85C30_1_CLOCK_X,
71    CONSOLE_DEFAULT_CONSOLE_CLOCK
72  },
73
74#if (HAS_PMC_PSC8)
75  {
76    SCORE603E_85C30_2_IRQ,
77    SCORE603E_85C30_2_CLOCK,
78    SCORE603E_85C30_2_CLOCK_X,
79    CONSOLE_DEFAULT_CONSOLE_CLOCK
80  },
81  {
82    SCORE603E_85C30_3_IRQ,
83    SCORE603E_85C30_3_CLOCK,
84    SCORE603E_85C30_3_CLOCK_X,
85    CONSOLE_DEFAULT_CONSOLE_CLOCK
86  },
87  {
88    SCORE603E_85C30_4_IRQ,
89    SCORE603E_85C30_4_CLOCK,
90    SCORE603E_85C30_4_CLOCK_X,
91    CONSOLE_DEFAULT_CONSOLE_CLOCK
92  },
93  {
94    SCORE603E_85C30_5_IRQ,
95    SCORE603E_85C30_5_CLOCK,
96    SCORE603E_85C30_5_CLOCK_X,
97    CONSOLE_DEFAULT_CONSOLE_CLOCK
98  },
99#endif
100
101};
102
103/*
104 * Table of port unique information for each port.
105 * See consolebsp.h for the Port_85C30_info structure defination.
106 */
107const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ] = {
108  {
109    (volatile unsigned char *) SCORE603E_85C30_CTRL_0,
110    (volatile unsigned char *) SCORE603E_85C30_DATA_0,
111    0x00,
112    &Protocols_85c30[0],
113    &Chips_85C30[0],
114  },
115  {
116    (volatile unsigned char *) SCORE603E_85C30_CTRL_1,
117    (volatile unsigned char *) SCORE603E_85C30_DATA_1,
118    0x01,
119    &Protocols_85c30[1],
120    &Chips_85C30[0],
121  },
122  {
123    (volatile unsigned char *) SCORE603E_85C30_CTRL_2,
124    (volatile unsigned char *) SCORE603E_85C30_DATA_2,
125    0x02,
126    &Protocols_85c30[2],
127    &Chips_85C30[1],
128  },
129  {
130    (volatile unsigned char *) SCORE603E_85C30_CTRL_3,
131    (volatile unsigned char *) SCORE603E_85C30_DATA_3,
132    0x03,
133    &Protocols_85c30[3],
134    &Chips_85C30[1],
135 },
136
137#if (HAS_PMC_PSC8)
138  {
139    (volatile unsigned char *) SCORE603E_85C30_CTRL_4,
140    (volatile unsigned char *) SCORE603E_85C30_DATA_4,
141    0x04,
142    &Protocols_85c30[4],
143    &Chips_85C30[2],
144 },
145 {
146    (volatile unsigned char *) SCORE603E_85C30_CTRL_5,
147    (volatile unsigned char *) SCORE603E_85C30_DATA_5,
148    0x05,
149    &Protocols_85c30[5],
150    &Chips_85C30[2],
151 },
152 {
153    (volatile unsigned char *) SCORE603E_85C30_CTRL_6,
154    (volatile unsigned char *) SCORE603E_85C30_DATA_6,
155    0x06,
156    &Protocols_85c30[6],
157    &Chips_85C30[3],
158 },
159 {
160    (volatile unsigned char *) SCORE603E_85C30_CTRL_7,
161    (volatile unsigned char *) SCORE603E_85C30_DATA_7,
162    0x07,
163    &Protocols_85c30[7],
164    &Chips_85C30[3],
165 },
166 {
167    (volatile unsigned char *) SCORE603E_85C30_CTRL_8,
168    (volatile unsigned char *) SCORE603E_85C30_DATA_8,
169    0x08,
170    &Protocols_85c30[8],
171    &Chips_85C30[4],
172 },
173 {
174    (volatile unsigned char *) SCORE603E_85C30_CTRL_9,
175    (volatile unsigned char *) SCORE603E_85C30_DATA_9,
176    0x09,
177    &Protocols_85c30[9],
178    &Chips_85C30[4],
179 },
180 {
181    (volatile unsigned char *) SCORE603E_85C30_CTRL_10,
182    (volatile unsigned char *) SCORE603E_85C30_DATA_10,
183    0x0a,
184    &Protocols_85c30[10],
185    &Chips_85C30[5],
186 },
187 {
188    (volatile unsigned char *) SCORE603E_85C30_CTRL_11,
189    (volatile unsigned char *) SCORE603E_85C30_DATA_11,
190    0x0b,
191    &Protocols_85c30[11],
192    &Chips_85C30[5],
193 },
194#endif
195};
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