1 | /* |
---|
2 | * This file contains the console driver chip level routines for the |
---|
3 | * z85c30 chip. |
---|
4 | * |
---|
5 | * Currently only polled mode is supported. |
---|
6 | * |
---|
7 | * COPYRIGHT (c) 1989-2009. |
---|
8 | * On-Line Applications Research Corporation (OAR). |
---|
9 | * |
---|
10 | * The license and distribution terms for this file may be |
---|
11 | * found in the file LICENSE in this distribution or at |
---|
12 | * http://www.rtems.com/license/LICENSE. |
---|
13 | * |
---|
14 | * $Id$ |
---|
15 | */ |
---|
16 | |
---|
17 | #include <rtems.h> |
---|
18 | #include <bsp.h> |
---|
19 | #include <rtems/libio.h> |
---|
20 | #include <assert.h> |
---|
21 | |
---|
22 | #include "85c30.h" |
---|
23 | #include "consolebsp.h" |
---|
24 | |
---|
25 | #define STATUS_REGISTER 0x00 |
---|
26 | #define DATA_REGISTER 0x08 |
---|
27 | |
---|
28 | #define Z8530_Status_Is_RX_character_available( _status ) \ |
---|
29 | ( (_status) & 0x01 ) |
---|
30 | |
---|
31 | #define Z8530_Status_Is_TX_buffer_empty( _status ) \ |
---|
32 | ( (_status) & 0x04 ) |
---|
33 | |
---|
34 | #define Z8530_Status_Is_break_abort( _status ) \ |
---|
35 | ( (_status) & 0x80 ) |
---|
36 | |
---|
37 | typedef struct { |
---|
38 | unsigned char read_setup; |
---|
39 | unsigned char write_setup; |
---|
40 | unsigned char mask_value; |
---|
41 | } char_size_info; |
---|
42 | |
---|
43 | static const char_size_info Char_size_85c30[] = { |
---|
44 | { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF }, |
---|
45 | { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F }, |
---|
46 | { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F }, |
---|
47 | { Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F } |
---|
48 | }; |
---|
49 | |
---|
50 | static const unsigned char Clock_speed_85c30[] = { |
---|
51 | Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK, Z8530_x64_CLOCK }; |
---|
52 | |
---|
53 | static const unsigned char Stop_bit_85c30[] = { |
---|
54 | Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 }; |
---|
55 | |
---|
56 | static const unsigned char Parity_85c30[] = { |
---|
57 | Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN }; |
---|
58 | |
---|
59 | /* PAGE |
---|
60 | * |
---|
61 | * Read_85c30_register |
---|
62 | * |
---|
63 | * Read a Z85c30 register |
---|
64 | */ |
---|
65 | static unsigned char Read_85c30_register( |
---|
66 | volatile unsigned char *csr, /* IN */ |
---|
67 | unsigned char register_number /* IN */ |
---|
68 | ) |
---|
69 | { |
---|
70 | unsigned char Data; |
---|
71 | |
---|
72 | *csr = register_number; |
---|
73 | |
---|
74 | rtems_bsp_delay_in_bus_cycles( 40 ); |
---|
75 | |
---|
76 | Data = *csr; |
---|
77 | |
---|
78 | rtems_bsp_delay_in_bus_cycles( 40 ); |
---|
79 | |
---|
80 | return Data; |
---|
81 | } |
---|
82 | |
---|
83 | /* |
---|
84 | * Write_85c30_register |
---|
85 | * |
---|
86 | * Write a Z85c30 register |
---|
87 | */ |
---|
88 | static void Write_85c30_register( |
---|
89 | volatile unsigned char *csr, /* IN */ |
---|
90 | unsigned char register_number, /* IN */ |
---|
91 | unsigned char data /* IN */ |
---|
92 | ) |
---|
93 | { |
---|
94 | *csr = register_number; |
---|
95 | |
---|
96 | rtems_bsp_delay_in_bus_cycles( 40 ); |
---|
97 | *csr = data; |
---|
98 | rtems_bsp_delay_in_bus_cycles( 40 ); |
---|
99 | } |
---|
100 | |
---|
101 | /* PAGE |
---|
102 | * |
---|
103 | * Reset_85c30_chip |
---|
104 | * |
---|
105 | * Reset a 85c30 chip. The pointers for the control registers for both |
---|
106 | * ports on the chip are used as input. |
---|
107 | */ |
---|
108 | void Reset_85c30_chip( |
---|
109 | volatile unsigned char *ctrl_0, /* IN */ |
---|
110 | volatile unsigned char *ctrl_1 /* IN */ |
---|
111 | ) |
---|
112 | { |
---|
113 | Write_85c30_register( ctrl_0, 0x09, 0x80 ); |
---|
114 | Write_85c30_register( ctrl_1, 0x09, 0x40 ); |
---|
115 | } |
---|
116 | |
---|
117 | /* PAGE |
---|
118 | * |
---|
119 | * initialize_85c30_port |
---|
120 | * |
---|
121 | * initialize a z85c30 Port |
---|
122 | */ |
---|
123 | void initialize_85c30_port( |
---|
124 | const Port_85C30_info *Port |
---|
125 | ) |
---|
126 | { |
---|
127 | uint16_t value; |
---|
128 | volatile unsigned char *ctrl; |
---|
129 | Console_Protocol *Setup; |
---|
130 | uint16_t baud_constant; |
---|
131 | |
---|
132 | Setup = Port->Protocol; |
---|
133 | ctrl = Port->ctrl; |
---|
134 | |
---|
135 | baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency, |
---|
136 | Port->Chip->clock_x, Setup->baud_rate ); |
---|
137 | |
---|
138 | /* |
---|
139 | * Using register 4 |
---|
140 | * Set up the clock rate. |
---|
141 | */ |
---|
142 | value = Clock_speed_85c30[ Port->Chip->clock_speed ] | |
---|
143 | Stop_bit_85c30[ Setup->stop_bits ] | |
---|
144 | Parity_85c30[ Setup->parity ]; |
---|
145 | Write_85c30_register( ctrl, 0x04, value ); |
---|
146 | |
---|
147 | /* |
---|
148 | * Set Write Register 1 to disable all interrupts |
---|
149 | */ |
---|
150 | Write_85c30_register( ctrl, 1, 0 ); |
---|
151 | |
---|
152 | #if CONSOLE_USE_INTERRUPTS |
---|
153 | /* |
---|
154 | * Set Write Register 2 to contain the interrupt vector |
---|
155 | */ |
---|
156 | Write_85c30_register( ctrl, 2, Port->Chip->vector ); |
---|
157 | #endif |
---|
158 | |
---|
159 | /* |
---|
160 | * Set Write Register 3 to disable the Receiver |
---|
161 | */ |
---|
162 | Write_85c30_register( ctrl, 0x03, 0x00 ); |
---|
163 | |
---|
164 | /* |
---|
165 | * Set Write Register 5 to disable the Transmitter |
---|
166 | */ |
---|
167 | Write_85c30_register( ctrl, 5, 0x00 ); |
---|
168 | |
---|
169 | /* WR 6 -- unneeded in asynchronous mode */ |
---|
170 | |
---|
171 | /* WR 7 -- unneeded in asynchronous mode */ |
---|
172 | |
---|
173 | /* |
---|
174 | * Set Write Register 9 to disable all interrupt sources |
---|
175 | */ |
---|
176 | Write_85c30_register( ctrl, 9, 0x00 ); |
---|
177 | |
---|
178 | /* |
---|
179 | * Set Write Register 10 for simple Asynchronous operation |
---|
180 | */ |
---|
181 | Write_85c30_register( ctrl, 0x0a, 0x00 ); |
---|
182 | |
---|
183 | /* |
---|
184 | * Setup the source of the receive and xmit |
---|
185 | * clock as BRG output and the transmit clock |
---|
186 | * as the output source for TRxC pin via register 11 |
---|
187 | */ |
---|
188 | Write_85c30_register( ctrl, 0x0b, 0x56 ); |
---|
189 | |
---|
190 | value = baud_constant; |
---|
191 | |
---|
192 | /* |
---|
193 | * Setup the lower 8 bits time constants = 1E. |
---|
194 | * If the time constans = 1E, then the desire |
---|
195 | * baud rate will be equilvalent to 9600, via register 12. |
---|
196 | */ |
---|
197 | Write_85c30_register( ctrl, 0x0c, value & 0xff ); |
---|
198 | |
---|
199 | /* |
---|
200 | * using register 13 |
---|
201 | * Setup the upper 8 bits time constants = 0 |
---|
202 | */ |
---|
203 | Write_85c30_register( ctrl, 0x0d, value>>8 ); |
---|
204 | |
---|
205 | /* |
---|
206 | * Set the DTR/REQ pin goes low when transmit |
---|
207 | * buffer becomes empty and enable the baud |
---|
208 | * rate generator enable with clock from the |
---|
209 | * SCC's PCLK input via register 14. |
---|
210 | */ |
---|
211 | Write_85c30_register( ctrl, 0x0e, 0x07 ); |
---|
212 | |
---|
213 | /* |
---|
214 | * Set Write Register 3 : Base Value is xx00_000x |
---|
215 | * D6 - D7 : Receive Character Length (configured) |
---|
216 | * D5 : Auto Enable (forced value) |
---|
217 | * D4 : Enter Hunt Phase (forced value) |
---|
218 | * D3 : Receive CRC Enable (forced value) |
---|
219 | * D2 : Address Search Mode (0 if not SDLC) (forced value) |
---|
220 | * D1 : Sync Character Load Inhibit (forced value) |
---|
221 | * D0 : Receiver Enable (configured) |
---|
222 | */ |
---|
223 | value = 0x01; |
---|
224 | value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup; |
---|
225 | |
---|
226 | Write_85c30_register( ctrl, 0x03, value ); |
---|
227 | |
---|
228 | /* |
---|
229 | * Set Write Register 5 : Base Value is 0xx0_x000 |
---|
230 | * D7 : Data Terminal Ready (DTR) (forced value) |
---|
231 | * D5 - D6 : Transmit Character Length (configured) |
---|
232 | * D4 : Send Break (forced value) |
---|
233 | * D3 : Transmitter Enable (configured) |
---|
234 | * D2 : CRC Select (forced value) |
---|
235 | * D1 : Request to Send (forced value) |
---|
236 | * D0 : Transmit CRC Enable (forced value) |
---|
237 | */ |
---|
238 | value = 0x8a; |
---|
239 | value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup; |
---|
240 | Write_85c30_register( ctrl, 0x05, value ); |
---|
241 | |
---|
242 | /* |
---|
243 | * Reset Tx UNDERRUN/EOM LATCH and ERROR |
---|
244 | * via register 0 |
---|
245 | */ |
---|
246 | Write_85c30_register( ctrl, 0x00, 0xf0 ); |
---|
247 | |
---|
248 | #if CONSOLE_USE_INTERRUPTS |
---|
249 | /* |
---|
250 | * Set Write Register 1 to interrupt on Rx characters or special condition. |
---|
251 | */ |
---|
252 | Write_85c30_register( ctrl, 1, 0x10 ); |
---|
253 | #endif |
---|
254 | |
---|
255 | /* |
---|
256 | * Set Write Register 15 to disable extended functions. |
---|
257 | */ |
---|
258 | |
---|
259 | Write_85c30_register( ctrl, 15, 0x00 ); |
---|
260 | |
---|
261 | /* |
---|
262 | * Set the Command Register to Reset Ext/STATUS. |
---|
263 | */ |
---|
264 | Write_85c30_register( ctrl, 0x00, 0x10 ); |
---|
265 | |
---|
266 | #if CONSOLE_USE_INTERRUPTS |
---|
267 | |
---|
268 | /* |
---|
269 | * Set Write Register 1 : Base Value is 0001_0110 |
---|
270 | * Enables Rx interrupt on all characters and special conditions. |
---|
271 | * Enables parity as a special condition. |
---|
272 | * Enables Tx interrupt. |
---|
273 | */ |
---|
274 | Write_85c30_register( ctrl, 1, 0x16 ); |
---|
275 | |
---|
276 | /* |
---|
277 | * Set Write Register 9 to enable all interrupt sources |
---|
278 | * Changed from 0 to a |
---|
279 | */ |
---|
280 | Write_85c30_register( ctrl, 9, 0x0A ); |
---|
281 | |
---|
282 | /* XXX */ |
---|
283 | |
---|
284 | /* |
---|
285 | * Issue reset highest Interrupt Under Service (IUS) command. |
---|
286 | */ |
---|
287 | Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 ); |
---|
288 | |
---|
289 | #endif |
---|
290 | |
---|
291 | } |
---|
292 | |
---|
293 | /* PAGE |
---|
294 | * |
---|
295 | * outbyte_polled_85c30 |
---|
296 | * |
---|
297 | * This routine transmits a character using polling. |
---|
298 | */ |
---|
299 | |
---|
300 | void outbyte_polled_85c30( |
---|
301 | volatile unsigned char *csr, /* IN */ |
---|
302 | char ch /* IN */ |
---|
303 | ) |
---|
304 | { |
---|
305 | unsigned char z8530_status; |
---|
306 | uint32_t isrlevel; |
---|
307 | |
---|
308 | rtems_interrupt_disable( isrlevel ); |
---|
309 | |
---|
310 | /* |
---|
311 | * Wait for the Transmit buffer to indicate that it is empty. |
---|
312 | */ |
---|
313 | do { |
---|
314 | z8530_status = Read_85c30_register( csr, STATUS_REGISTER ); |
---|
315 | } while ( !Z8530_Status_Is_TX_buffer_empty( z8530_status ) ); |
---|
316 | |
---|
317 | /* |
---|
318 | * Write the character. |
---|
319 | */ |
---|
320 | Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch ); |
---|
321 | |
---|
322 | rtems_interrupt_enable( isrlevel ); |
---|
323 | } |
---|
324 | |
---|
325 | /* PAGE |
---|
326 | * |
---|
327 | * inbyte_nonblocking_85c30 |
---|
328 | * |
---|
329 | * This routine polls for a character. |
---|
330 | */ |
---|
331 | |
---|
332 | int inbyte_nonblocking_85c30( |
---|
333 | const Port_85C30_info *Port |
---|
334 | ) |
---|
335 | { |
---|
336 | volatile unsigned char *csr; |
---|
337 | unsigned char z8530_status; |
---|
338 | uint8_t data; |
---|
339 | |
---|
340 | csr = Port->ctrl; |
---|
341 | |
---|
342 | /* |
---|
343 | * return -1 if a character is not available. |
---|
344 | */ |
---|
345 | z8530_status = Read_85c30_register( csr, STATUS_REGISTER ); |
---|
346 | if ( !Z8530_Status_Is_RX_character_available( z8530_status ) ) |
---|
347 | return -1; |
---|
348 | |
---|
349 | /* |
---|
350 | * Return the character read. |
---|
351 | */ |
---|
352 | data = Read_85c30_register( csr, DATA_REGISTER ); |
---|
353 | data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value; |
---|
354 | |
---|
355 | return data; |
---|
356 | } |
---|
357 | |
---|
358 | /* |
---|
359 | * Interrupt driven console IO |
---|
360 | */ |
---|
361 | |
---|
362 | #if CONSOLE_USE_INTERRUPTS |
---|
363 | |
---|
364 | /*PAGE |
---|
365 | * |
---|
366 | * Z8530_Async_Channel_ISR |
---|
367 | * |
---|
368 | */ |
---|
369 | /* RR0 */ |
---|
370 | |
---|
371 | rtems_isr ISR_85c30_Async( |
---|
372 | const Port_85C30_info *Port |
---|
373 | ) |
---|
374 | { |
---|
375 | uint16_t status; |
---|
376 | volatile Console_Protocol *Protocol; |
---|
377 | unsigned char data; |
---|
378 | bool did_something = false; |
---|
379 | |
---|
380 | Protocol = Port->Protocol; |
---|
381 | |
---|
382 | status = Read_85c30_register( Port->ctrl, 0x00 ); |
---|
383 | |
---|
384 | /* |
---|
385 | * Was this a RX interrupt? If so, then process it. |
---|
386 | */ |
---|
387 | |
---|
388 | if ( Z8530_Status_Is_RX_character_available( status ) ) { |
---|
389 | data = Read_85c30_register( Port->ctrl, DATA_REGISTER ); |
---|
390 | data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value; |
---|
391 | |
---|
392 | rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data, |
---|
393 | &data, 1 ); |
---|
394 | did_something = true; |
---|
395 | } |
---|
396 | |
---|
397 | /* |
---|
398 | * Was this a TX empty interrupt? If so, then process it. |
---|
399 | */ |
---|
400 | |
---|
401 | if (Z8530_Status_Is_TX_buffer_empty( status ) ) { |
---|
402 | if ( !Ring_buffer_Is_empty( &Protocol->TX_Buffer ) ) { |
---|
403 | Ring_buffer_Remove_character( &Protocol->TX_Buffer, data ); |
---|
404 | Write_85c30_register( Port->ctrl, DATA_REGISTER, data ); |
---|
405 | |
---|
406 | } else { |
---|
407 | Protocol->Is_TX_active = false; |
---|
408 | Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x28 ); |
---|
409 | } |
---|
410 | |
---|
411 | did_something = true; |
---|
412 | } |
---|
413 | |
---|
414 | /* |
---|
415 | * Issue reset highest Interrupt Under Service (IUS) command. |
---|
416 | */ |
---|
417 | |
---|
418 | /* |
---|
419 | if ( did_something ) |
---|
420 | */ |
---|
421 | Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 ); |
---|
422 | } |
---|
423 | |
---|
424 | #endif |
---|