[9c448e1] | 1 | /* |
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[6128a4a] | 2 | * This file contains the console driver chip level routines for the |
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[9c448e1] | 3 | * z85c30 chip. |
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| 4 | * |
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| 5 | * Currently only polled mode is supported. |
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| 6 | * |
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[40e7ae2] | 7 | * COPYRIGHT (c) 1989-2008. |
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[9c448e1] | 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[b14e2f2] | 12 | * http://www.rtems.com/license/LICENSE. |
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[9c448e1] | 13 | * |
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[6128a4a] | 14 | * $Id: |
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[9c448e1] | 15 | */ |
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| 16 | |
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| 17 | #include <rtems.h> |
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| 18 | #include <bsp.h> |
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| 19 | #include <rtems/libio.h> |
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| 20 | #include <assert.h> |
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| 21 | |
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| 22 | #include "85c30.h" |
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| 23 | #include "consolebsp.h" |
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| 24 | |
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| 25 | #define STATUS_REGISTER 0x00 |
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| 26 | #define DATA_REGISTER 0x08 |
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| 27 | |
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| 28 | #define Z8530_Status_Is_RX_character_available( _status ) \ |
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| 29 | ( (_status) & 0x01 ) |
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| 30 | |
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| 31 | #define Z8530_Status_Is_TX_buffer_empty( _status ) \ |
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| 32 | ( (_status) & 0x04 ) |
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| 33 | |
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| 34 | #define Z8530_Status_Is_break_abort( _status ) \ |
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| 35 | ( (_status) & 0x80 ) |
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| 36 | |
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| 37 | typedef struct { |
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| 38 | unsigned char read_setup; |
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| 39 | unsigned char write_setup; |
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| 40 | unsigned char mask_value; |
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| 41 | } char_size_info; |
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| 42 | |
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| 43 | static const char_size_info Char_size_85c30[] = { |
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[6128a4a] | 44 | { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF }, |
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| 45 | { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F }, |
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| 46 | { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F }, |
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[9c448e1] | 47 | { Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F } |
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| 48 | }; |
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| 49 | |
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[6128a4a] | 50 | static const unsigned char Clock_speed_85c30[] = { |
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[9c448e1] | 51 | Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK, Z8530_x64_CLOCK }; |
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| 52 | |
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[6128a4a] | 53 | static const unsigned char Stop_bit_85c30[] = { |
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[9c448e1] | 54 | Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 }; |
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| 55 | |
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[6128a4a] | 56 | static const unsigned char Parity_85c30[] = { |
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[9c448e1] | 57 | Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN }; |
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| 58 | |
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| 59 | /* PAGE |
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| 60 | * |
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| 61 | * Read_85c30_register |
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| 62 | * |
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| 63 | * Read a Z85c30 register |
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| 64 | */ |
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[6128a4a] | 65 | static unsigned char Read_85c30_register( |
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[9c448e1] | 66 | volatile unsigned char *csr, /* IN */ |
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| 67 | unsigned char register_number /* IN */ |
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| 68 | ) |
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| 69 | { |
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| 70 | unsigned char Data; |
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[6128a4a] | 71 | |
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| 72 | *csr = register_number; |
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[9c448e1] | 73 | |
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[3d5bd91b] | 74 | rtems_bsp_delay_in_bus_cycles( 40 ); |
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[9c448e1] | 75 | |
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| 76 | Data = *csr; |
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[6128a4a] | 77 | |
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[3d5bd91b] | 78 | rtems_bsp_delay_in_bus_cycles( 40 ); |
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[9c448e1] | 79 | |
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| 80 | return Data; |
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| 81 | } |
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| 82 | |
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| 83 | /* |
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| 84 | * Write_85c30_register |
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| 85 | * |
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| 86 | * Write a Z85c30 register |
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| 87 | */ |
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| 88 | static void Write_85c30_register( |
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| 89 | volatile unsigned char *csr, /* IN */ |
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| 90 | unsigned char register_number, /* IN */ |
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| 91 | unsigned char data /* IN */ |
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| 92 | ) |
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| 93 | { |
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| 94 | *csr = register_number; |
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| 95 | |
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[3d5bd91b] | 96 | rtems_bsp_delay_in_bus_cycles( 40 ); |
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[9c448e1] | 97 | *csr = data; |
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[3d5bd91b] | 98 | rtems_bsp_delay_in_bus_cycles( 40 ); |
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[9c448e1] | 99 | } |
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| 100 | |
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| 101 | /* PAGE |
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| 102 | * |
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| 103 | * Reset_85c30_chip |
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| 104 | * |
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| 105 | * Reset a 85c30 chip. The pointers for the control registers for both |
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| 106 | * ports on the chip are used as input. |
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| 107 | */ |
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| 108 | void Reset_85c30_chip( |
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| 109 | volatile unsigned char *ctrl_0, /* IN */ |
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| 110 | volatile unsigned char *ctrl_1 /* IN */ |
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| 111 | ) |
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| 112 | { |
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| 113 | Write_85c30_register( ctrl_0, 0x09, 0x80 ); |
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| 114 | Write_85c30_register( ctrl_1, 0x09, 0x40 ); |
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| 115 | } |
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[6128a4a] | 116 | |
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[9c448e1] | 117 | /* PAGE |
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| 118 | * |
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| 119 | * initialize_85c30_port |
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| 120 | * |
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| 121 | * initialize a z85c30 Port |
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| 122 | */ |
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| 123 | void initialize_85c30_port( |
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| 124 | const Port_85C30_info *Port |
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| 125 | ) |
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| 126 | { |
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[dac4208] | 127 | uint16_t value; |
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[9c448e1] | 128 | volatile unsigned char *ctrl; |
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| 129 | Console_Protocol *Setup; |
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[dac4208] | 130 | uint16_t baud_constant; |
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[9c448e1] | 131 | |
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[40e7ae2] | 132 | printk("initialize_85c30_port start\n"); |
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| 133 | |
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[9c448e1] | 134 | Setup = Port->Protocol; |
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| 135 | ctrl = Port->ctrl; |
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| 136 | |
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[6128a4a] | 137 | baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency, |
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[9c448e1] | 138 | Port->Chip->clock_x, Setup->baud_rate ); |
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| 139 | |
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| 140 | /* |
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| 141 | * Using register 4 |
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| 142 | * Set up the clock rate. |
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| 143 | */ |
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| 144 | value = Clock_speed_85c30[ Port->Chip->clock_speed ] | |
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| 145 | Stop_bit_85c30[ Setup->stop_bits ] | |
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| 146 | Parity_85c30[ Setup->parity ]; |
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| 147 | Write_85c30_register( ctrl, 0x04, value ); |
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| 148 | |
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| 149 | /* |
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| 150 | * Set Write Register 1 to disable all interrupts |
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| 151 | */ |
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| 152 | Write_85c30_register( ctrl, 1, 0 ); |
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| 153 | |
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| 154 | #if CONSOLE_USE_INTERRUPTS |
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| 155 | /* |
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| 156 | * Set Write Register 2 to contain the interrupt vector |
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| 157 | */ |
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[40e7ae2] | 158 | printk("initialize_85c30_port 2, %d\n", Port->Chip->vector ); |
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[9c448e1] | 159 | Write_85c30_register( ctrl, 2, Port->Chip->vector ); |
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| 160 | #endif |
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| 161 | |
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| 162 | /* |
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| 163 | * Set Write Register 3 to disable the Receiver |
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| 164 | */ |
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[40e7ae2] | 165 | printk("initialize_85c30_port 0x03, 0x00\n"); |
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[9c448e1] | 166 | Write_85c30_register( ctrl, 0x03, 0x00 ); |
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| 167 | |
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| 168 | /* |
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| 169 | * Set Write Register 5 to disable the Transmitter |
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| 170 | */ |
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[40e7ae2] | 171 | printk("initialize_85c30_port 5, 0x00\n"); |
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[9c448e1] | 172 | Write_85c30_register( ctrl, 5, 0x00 ); |
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| 173 | |
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| 174 | /* WR 6 -- unneeded in asynchronous mode */ |
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| 175 | |
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| 176 | /* WR 7 -- unneeded in asynchronous mode */ |
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| 177 | |
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| 178 | /* |
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| 179 | * Set Write Register 9 to disable all interrupt sources |
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| 180 | */ |
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[40e7ae2] | 181 | printk("initialize_85c30_port 9, 0x00\n"); |
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[9c448e1] | 182 | Write_85c30_register( ctrl, 9, 0x00 ); |
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| 183 | |
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| 184 | /* |
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| 185 | * Set Write Register 10 for simple Asynchronous operation |
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| 186 | */ |
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[40e7ae2] | 187 | printk("initialize_85c30_port 0x0a, 0x00\n"); |
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[9c448e1] | 188 | Write_85c30_register( ctrl, 0x0a, 0x00 ); |
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| 189 | |
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| 190 | /* |
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| 191 | * Setup the source of the receive and xmit |
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| 192 | * clock as BRG output and the transmit clock |
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| 193 | * as the output source for TRxC pin via register 11 |
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| 194 | */ |
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[40e7ae2] | 195 | printk("initialize_85c30_port 0x0b, 0x56\n"); |
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[9c448e1] | 196 | Write_85c30_register( ctrl, 0x0b, 0x56 ); |
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| 197 | |
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| 198 | value = baud_constant; |
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| 199 | |
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| 200 | /* |
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| 201 | * Setup the lower 8 bits time constants = 1E. |
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| 202 | * If the time constans = 1E, then the desire |
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| 203 | * baud rate will be equilvalent to 9600, via register 12. |
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| 204 | */ |
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[40e7ae2] | 205 | printk("initialize_85c30_port 0x0c, 0x%x\n", value & 0xff); |
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[9c448e1] | 206 | Write_85c30_register( ctrl, 0x0c, value & 0xff ); |
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| 207 | |
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| 208 | /* |
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| 209 | * using register 13 |
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| 210 | * Setup the upper 8 bits time constants = 0 |
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| 211 | */ |
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[40e7ae2] | 212 | printk("initialize_85c30_port 0x0d, 0x%x\n", value>>8); |
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[9c448e1] | 213 | Write_85c30_register( ctrl, 0x0d, value>>8 ); |
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| 214 | |
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| 215 | /* |
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| 216 | * Set the DTR/REQ pin goes low when transmit |
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| 217 | * buffer becomes empty and enable the baud |
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| 218 | * rate generator enable with clock from the |
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| 219 | * SCC's PCLK input via register 14. |
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| 220 | */ |
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[40e7ae2] | 221 | printk("initialize_85c30_port 0x0e, 0x07\n"); |
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[9c448e1] | 222 | Write_85c30_register( ctrl, 0x0e, 0x07 ); |
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| 223 | |
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| 224 | /* |
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| 225 | * Set Write Register 3 : Base Value is xx00_000x |
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| 226 | * D6 - D7 : Receive Character Length (configured) |
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| 227 | * D5 : Auto Enable (forced value) |
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| 228 | * D4 : Enter Hunt Phase (forced value) |
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| 229 | * D3 : Receive CRC Enable (forced value) |
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| 230 | * D2 : Address Search Mode (0 if not SDLC) (forced value) |
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| 231 | * D1 : Sync Character Load Inhibit (forced value) |
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| 232 | * D0 : Receiver Enable (configured) |
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| 233 | */ |
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| 234 | value = 0x01; |
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| 235 | value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup; |
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| 236 | |
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[40e7ae2] | 237 | printk("initialize_85c30_port 0x03, 0x%x\n", value); |
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[9c448e1] | 238 | Write_85c30_register( ctrl, 0x03, value ); |
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| 239 | |
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| 240 | /* |
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| 241 | * Set Write Register 5 : Base Value is 0xx0_x000 |
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| 242 | * D7 : Data Terminal Ready (DTR) (forced value) |
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| 243 | * D5 - D6 : Transmit Character Length (configured) |
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| 244 | * D4 : Send Break (forced value) |
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| 245 | * D3 : Transmitter Enable (configured) |
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| 246 | * D2 : CRC Select (forced value) |
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| 247 | * D1 : Request to Send (forced value) |
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| 248 | * D0 : Transmit CRC Enable (forced value) |
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| 249 | */ |
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| 250 | value = 0x8a; |
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| 251 | value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup; |
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[40e7ae2] | 252 | printk("initialize_85c30_port 0x05, 0x%x\n", value); |
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[9c448e1] | 253 | Write_85c30_register( ctrl, 0x05, value ); |
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[6128a4a] | 254 | |
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[9c448e1] | 255 | /* |
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| 256 | * Reset Tx UNDERRUN/EOM LATCH and ERROR |
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[6128a4a] | 257 | * via register 0 |
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[9c448e1] | 258 | */ |
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[40e7ae2] | 259 | printk("initialize_85c30_port 0x00, 0xf0\n"); |
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[9c448e1] | 260 | Write_85c30_register( ctrl, 0x00, 0xf0 ); |
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[6128a4a] | 261 | |
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[9c448e1] | 262 | #if CONSOLE_USE_INTERRUPTS |
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| 263 | /* |
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| 264 | * Set Write Register 1 to interrupt on Rx characters or special condition. |
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| 265 | */ |
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[40e7ae2] | 266 | printk("initialize_85c30_port 1, 0x10\n"); |
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[9c448e1] | 267 | Write_85c30_register( ctrl, 1, 0x10 ); |
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| 268 | #endif |
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| 269 | |
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| 270 | /* |
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| 271 | * Set Write Register 15 to disable extended functions. |
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| 272 | */ |
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| 273 | |
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[40e7ae2] | 274 | printk("initialize_85c30_port 15, 0x00\n"); |
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[9c448e1] | 275 | Write_85c30_register( ctrl, 15, 0x00 ); |
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| 276 | |
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| 277 | /* |
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| 278 | * Set the Command Register to Reset Ext/STATUS. |
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| 279 | */ |
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[40e7ae2] | 280 | printk("initialize_85c30_port 0x00, 0x10\n"); |
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[9c448e1] | 281 | Write_85c30_register( ctrl, 0x00, 0x10 ); |
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| 282 | |
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| 283 | #if CONSOLE_USE_INTERRUPTS |
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| 284 | |
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| 285 | /* |
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| 286 | * Set Write Register 1 : Base Value is 0001_0110 |
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| 287 | * Enables Rx interrupt on all characters and special conditions. |
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| 288 | * Enables parity as a special condition. |
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| 289 | * Enables Tx interrupt. |
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| 290 | */ |
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[40e7ae2] | 291 | printk("initialize_85c30_port 1, 0x16\n"); |
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[9c448e1] | 292 | Write_85c30_register( ctrl, 1, 0x16 ); |
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| 293 | |
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| 294 | /* |
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| 295 | * Set Write Register 9 to enable all interrupt sources |
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| 296 | * Changed from 0 to a |
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| 297 | */ |
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[40e7ae2] | 298 | printk("initialize_85c30_port 9, 0x0A\n"); |
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[9c448e1] | 299 | Write_85c30_register( ctrl, 9, 0x0A ); |
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| 300 | |
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| 301 | /* XXX */ |
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| 302 | |
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| 303 | /* |
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| 304 | * Issue reset highest Interrupt Under Service (IUS) command. |
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| 305 | */ |
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[40e7ae2] | 306 | printk("initialize_85c30_port STATUS_REGISTER, 0X38\n"); |
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[9c448e1] | 307 | Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 ); |
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| 308 | |
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| 309 | #endif |
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| 310 | |
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[40e7ae2] | 311 | printk("initialize_85c30_port end of method\n"); |
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[9c448e1] | 312 | } |
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| 313 | |
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| 314 | /* PAGE |
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| 315 | * |
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| 316 | * outbyte_polled_85c30 |
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| 317 | * |
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| 318 | * This routine transmits a character using polling. |
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| 319 | */ |
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| 320 | |
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| 321 | void outbyte_polled_85c30( |
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| 322 | volatile unsigned char *csr, /* IN */ |
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| 323 | char ch /* IN */ |
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| 324 | ) |
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| 325 | { |
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| 326 | unsigned char z8530_status; |
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[dac4208] | 327 | uint32_t isrlevel; |
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[6128a4a] | 328 | |
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[9c448e1] | 329 | rtems_interrupt_disable( isrlevel ); |
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| 330 | |
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| 331 | /* |
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| 332 | * Wait for the Transmit buffer to indicate that it is empty. |
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| 333 | */ |
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| 334 | do { |
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| 335 | z8530_status = Read_85c30_register( csr, STATUS_REGISTER ); |
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| 336 | } while ( !Z8530_Status_Is_TX_buffer_empty( z8530_status ) ); |
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| 337 | |
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| 338 | /* |
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| 339 | * Write the character. |
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| 340 | */ |
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[6128a4a] | 341 | Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch ); |
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[9c448e1] | 342 | |
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| 343 | rtems_interrupt_enable( isrlevel ); |
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| 344 | } |
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| 345 | |
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| 346 | /* PAGE |
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| 347 | * |
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| 348 | * inbyte_nonblocking_85c30 |
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| 349 | * |
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| 350 | * This routine polls for a character. |
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| 351 | */ |
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| 352 | |
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[6128a4a] | 353 | int inbyte_nonblocking_85c30( |
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[9c448e1] | 354 | const Port_85C30_info *Port |
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| 355 | ) |
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| 356 | { |
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| 357 | volatile unsigned char *csr; |
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| 358 | unsigned char z8530_status; |
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[dac4208] | 359 | uint8_t data; |
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[9c448e1] | 360 | |
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| 361 | csr = Port->ctrl; |
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| 362 | |
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| 363 | /* |
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| 364 | * return -1 if a character is not available. |
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| 365 | */ |
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| 366 | z8530_status = Read_85c30_register( csr, STATUS_REGISTER ); |
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| 367 | if ( !Z8530_Status_Is_RX_character_available( z8530_status ) ) |
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| 368 | return -1; |
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[6128a4a] | 369 | |
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[9c448e1] | 370 | /* |
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| 371 | * Return the character read. |
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| 372 | */ |
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| 373 | data = Read_85c30_register( csr, DATA_REGISTER ); |
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| 374 | data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value; |
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| 375 | |
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| 376 | return data; |
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| 377 | } |
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| 378 | |
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| 379 | /* |
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| 380 | * Interrupt driven console IO |
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| 381 | */ |
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| 382 | |
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| 383 | #if CONSOLE_USE_INTERRUPTS |
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| 384 | |
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| 385 | /*PAGE |
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| 386 | * |
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| 387 | * Z8530_Async_Channel_ISR |
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| 388 | * |
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| 389 | */ |
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| 390 | /* RR0 */ |
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| 391 | |
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| 392 | rtems_isr ISR_85c30_Async( |
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| 393 | const Port_85C30_info *Port |
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| 394 | ) |
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| 395 | { |
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[dac4208] | 396 | uint16_t status; |
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[9c448e1] | 397 | volatile Console_Protocol *Protocol; |
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| 398 | unsigned char data; |
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[3551166d] | 399 | bool did_something = false; |
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[9c448e1] | 400 | |
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| 401 | Protocol = Port->Protocol; |
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| 402 | |
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| 403 | status = Read_85c30_register( Port->ctrl, 0x00 ); |
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| 404 | |
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| 405 | /* |
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| 406 | * Was this a RX interrupt? If so, then process it. |
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| 407 | */ |
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| 408 | |
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| 409 | if ( Z8530_Status_Is_RX_character_available( status ) ) { |
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| 410 | data = Read_85c30_register( Port->ctrl, DATA_REGISTER ); |
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| 411 | data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value; |
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[6128a4a] | 412 | |
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[9c448e1] | 413 | rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data, |
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| 414 | &data, 1 ); |
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[3551166d] | 415 | did_something = true; |
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[9c448e1] | 416 | } |
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| 417 | |
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| 418 | /* |
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| 419 | * Was this a TX empty interrupt? If so, then process it. |
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| 420 | */ |
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| 421 | |
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| 422 | if (Z8530_Status_Is_TX_buffer_empty( status ) ) { |
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| 423 | if ( !Ring_buffer_Is_empty( &Protocol->TX_Buffer ) ) { |
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| 424 | Ring_buffer_Remove_character( &Protocol->TX_Buffer, data ); |
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| 425 | Write_85c30_register( Port->ctrl, DATA_REGISTER, data ); |
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| 426 | |
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| 427 | } else { |
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[3551166d] | 428 | Protocol->Is_TX_active = false; |
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[9c448e1] | 429 | Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x28 ); |
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| 430 | } |
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| 431 | |
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[3551166d] | 432 | did_something = true; |
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[9c448e1] | 433 | } |
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| 434 | |
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| 435 | /* |
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| 436 | * Issue reset highest Interrupt Under Service (IUS) command. |
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| 437 | */ |
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| 438 | |
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| 439 | /* |
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| 440 | if ( did_something ) |
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| 441 | */ |
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| 442 | Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 ); |
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| 443 | } |
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| 444 | |
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| 445 | #endif |
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