4.104.114.84.95
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1 | # |
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2 | # $Id$ |
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3 | # |
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4 | |
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5 | BSP NAME: score603e |
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6 | BOARD: VISTA SCORE 603e Generation I and II |
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7 | BUS: N/A |
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8 | CPU FAMILY: ppc |
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9 | CPU: PowerPC 603e |
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10 | COPROCESSORS: N/A |
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11 | MODE: 32 bit mode |
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12 | |
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13 | DEBUG MONITOR: see note. |
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14 | |
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15 | PERIPHERALS |
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16 | =========== |
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17 | TIMERS: PPC internal Timebase register |
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18 | RESOLUTION: |
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19 | SERIAL PORTS: 2 Z85C30s |
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20 | REAL-TIME CLOCK: Generation I: SGSM48T18 |
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21 | Generation II: ICM7170AIBG |
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22 | DMA: none |
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23 | VIDEO: none |
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24 | SCSI: none |
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25 | NETWORKING: none |
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26 | |
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27 | DRIVER INFORMATION |
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28 | ================== |
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29 | CLOCK DRIVER: PPC internal |
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30 | IOSUPP DRIVER: N/A |
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31 | SHMSUPP: N/A |
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32 | TIMER DRIVER: PPC internal |
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33 | TTY DRIVER: PPC internal |
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34 | |
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35 | STDIO |
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36 | ===== |
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37 | PORT: Console port 0 |
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38 | ELECTRICAL: na |
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39 | BAUD: 9600 |
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40 | BITS PER CHARACTER: 8 |
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41 | PARITY: n |
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42 | STOP BITS: 1 |
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43 | |
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44 | Notes |
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45 | ===== |
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46 | |
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47 | This BSP has been tested using any Rom monitor. There have |
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48 | been three rom chips loaded on the boards. One with the SDS |
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49 | debug monitor, one with the firmworks monitor, and one with |
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50 | the OAR Boot chip. The OAR Boot chip contains the basic |
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51 | initialization from the SDS debugger and a jump to flash |
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52 | location 0x04001200. |
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53 | |
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54 | The compiler option SCORE603E_GENERATION is set to 1 or 2, |
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55 | for the generation to be produced. |
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