source: rtems/c/src/lib/libbsp/powerpc/score603e/README @ 196094eb

4.104.114.84.95
Last change on this file since 196094eb was 9c448e1, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 19, 1999 at 12:22:33 AM

BSP for Vista Score603e added.

  • Property mode set to 100644
File size: 1.3 KB
Line 
1#
2#  $Id$
3#
4
5BSP NAME:           score603e
6BOARD:              VISTA SCORE 603e Generation I and II
7BUS:                N/A
8CPU FAMILY:         ppc
9CPU:                PowerPC 603e
10COPROCESSORS:       N/A
11MODE:               32 bit mode
12
13DEBUG MONITOR:      see note.
14
15PERIPHERALS
16===========
17TIMERS:             PPC internal Timebase register
18  RESOLUTION:         
19SERIAL PORTS:       2 Z85C30s
20REAL-TIME CLOCK:    Generation  I: SGSM48T18
21                    Generation II: ICM7170AIBG
22DMA:                none
23VIDEO:              none
24SCSI:               none
25NETWORKING:         none
26
27DRIVER INFORMATION
28==================
29CLOCK DRIVER:       PPC internal
30IOSUPP DRIVER:      N/A
31SHMSUPP:            N/A
32TIMER DRIVER:       PPC internal
33TTY DRIVER:         PPC internal
34
35STDIO
36=====
37PORT:               Console port 0
38ELECTRICAL:         na
39BAUD:               9600
40BITS PER CHARACTER: 8
41PARITY:             n
42STOP BITS:          1
43
44Notes
45=====
46
47This BSP has been tested using any Rom monitor.  There have
48been three rom chips loaded on the boards.  One with the SDS
49debug monitor, one with the firmworks monitor, and one with
50the OAR Boot chip.  The OAR Boot chip contains the basic
51initialization from the SDS debugger and a jump to flash
52location 0x04001200.
53
54The compiler option SCORE603E_GENERATION is set to 1 or 2,
55for the generation to be produced.
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