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source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c @ dac4208

4.104.114.84.95

Last change on this file since dac4208 was dac4208, checked in by Ralf Corsepius <ralf.corsepius@…>, on 03/31/04 at 03:47:07

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, clock/clock.c, console/85c30.c, console/console.c, console/consolebsp.h, include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c, startup/bspstart.c, startup/genpvec.c, startup/spurious.c, startup/vmeintr.c, timer/timer.c, tod/tod.c: Convert to using c99 fixed size types.

Property mode set to 100644

File size: 12.7 KB

Line
1	/*
2	*
3	* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
4	* On-Line Applications Research Corporation (OAR).
5	*
6	* $Id$
7	*/
8
9	#include <rtems.h>
10	#include <assert.h>
11	#include <stdio.h>
12
13	#include <bsp.h>
14	#include "PCI.h"
15
16	/********************************************************************
17	********************************************************************
18	******* *******
19	******* Prototypes *******
20	******* *******
21	********************************************************************
22	********************************************************************/
23
24
25	/********************************************************************
26	********************************************************************
27	******* *******
28	******* *******
29	******* *******
30	********************************************************************
31	********************************************************************/
32
33	typedef struct {
34	uint32_t PCI_ID; /* 0x80030000 */
35	uint32_t PCI_CSR; /* 0x80030004 */
36	uint32_t PCI_CLASS; /* 0x80030008 */
37	uint32_t PCI_MISC0; /* 0x8003000C */
38	uint32_t PCI_BS; /* 0x80030010 */
39	uint32_t Buf_0x80030014[ 0x0A ]; /* 0x80030014 */
40	uint32_t PCI_MISC1; /* 0x8003003C */
41	uint32_t Buf_0x80030040[ 0x30 ]; /* 0x80030040 */
42	uint32_t LSI0_CTL; /* 0x80030100 */
43	uint32_t LSI0_BS; /* 0x80030104 */
44	uint32_t LSI0_BD; /* 0x80030108 */
45	uint32_t LSI0_TO; /* 0x8003010C */
46	uint32_t Buf_0x80030110; /* 0x80030110 */
47	uint32_t LSI1_CTL; /* 0x80030114 */
48	uint32_t LSI1_BS; /* 0x80030118 */
49	uint32_t LSI1_BD; /* 0x8003011C */
50	uint32_t LSI1_TO; /* 0x80030120 */
51	uint32_t Buf_0x80030124; /* 0x80030124 */
52	uint32_t LSI2_CTL; /* 0x80030128 */
53	uint32_t LSI2_BS; /* 0x8003012C */
54	uint32_t LSI2_BD; /* 0x80030130 */
55	uint32_t LSI2_TO; /* 0x80030134 */
56	uint32_t Buf_0x80030138; /* 0x80030138 */
57	uint32_t LSI3_CTL; /* 0x8003013C */
58	uint32_t LSI3_BS; /* 0x80030140 */
59	uint32_t LSI3_BD; /* 0x80030144 */
60	uint32_t LSI3_TO; /* 0x80030148 */
61	uint32_t Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */
62	uint32_t SCYC_CTL; /* 0x80030170 */
63	uint32_t SCYC_ADDR; /* 0x80030174 */
64	uint32_t SCYC_EN; /* 0x80030178 */
65	uint32_t SCYC_CMP; /* 0x8003017C */
66	uint32_t SCYC_SWP; /* 0x80030180 */
67	uint32_t LMISC; /* 0x80030184 */
68	uint32_t SLSI; /* 0x80030188 */
69	uint32_t L_CMDERR; /* 0x8003018C */
70	uint32_t LAERR; /* 0x80030190 */
71	uint32_t Buf_0x80030194[ 0x1B ]; /* 0x80030194 */
72	uint32_t DCTL; /* 0x80030200 */
73	uint32_t DTBC; /* 0x80030204 */
74	uint32_t DLA; /* 0x80030208 */
75	uint32_t Buf_0x8003020C; /* 0x8003020C */
76	uint32_t DVA; /* 0x80030210 */
77	uint32_t Buf_0x80030214; /* 0x80030214 */
78	uint32_t DCPP; /* 0x80030218 */
79	uint32_t Buf_0x8003021C; /* 0x8003021C */
80	uint32_t DGCS; /* 0x80030220 */
81	uint32_t D_LLUE; /* 0x80030224 */
82	uint32_t Buf_0x80030228[ 0x36 ]; /* 0x80030228 */
83	uint32_t LINT_EN; /* 0x80030300 */
84	uint32_t LINT_STAT; /* 0x80030304 */
85	uint32_t LINT_MAP0; /* 0x80030308 */
86	uint32_t LINT_MAP1; /* 0x8003030C */
87	uint32_t VINT_EN; /* 0x80030310 */
88	uint32_t VINT_STAT; /* 0x80030314 */
89	uint32_t VINT_MAP0; /* 0x80030318 */
90	uint32_t VINT_MAP1; /* 0x8003031C */
91	uint32_t STATID; /* 0x80030320 */
92	uint32_t V1_STATID; /* 0x80030324 */
93	uint32_t V2_STATID; /* 0x80030328 */
94	uint32_t V3_STATID; /* 0x8003032C */
95	uint32_t V4_STATID; /* 0x80030330 */
96	uint32_t V5_STATID; /* 0x80030334 */
97	uint32_t V6_STATID; /* 0x80030338 */
98	uint32_t V7_STATID; /* 0x8003033C */
99	uint32_t Buf_0x80030340[ 0x30 ]; /* 0x80030340 */
100	uint32_t MAST_CTL; /* 0x80030400 */
101	uint32_t MISC_CTL; /* 0x80030404 */
102	uint32_t MISC_STAT; /* 0x80030408 */
103	uint32_t USER_AM; /* 0x8003040C */
104	uint32_t Buf_0x80030410[ 0x2bc ];/* 0x80030410 */
105	uint32_t VSI0_CTL; /* 0x80030F00 */
106	uint32_t VSI0_BS; /* 0x80030F04 */
107	uint32_t VSI0_BD; /* 0x80030F08 */
108	uint32_t VSI0_TO; /* 0x80030F0C */
109	uint32_t Buf_0x80030f10; /* 0x80030F10 */
110	uint32_t VSI1_CTL; /* 0x80030F14 */
111	uint32_t VSI1_BS; /* 0x80030F18 */
112	uint32_t VSI1_BD; /* 0x80030F1C */
113	uint32_t VSI1_TO; /* 0x80030F20 */
114	uint32_t Buf_0x80030F24; /* 0x80030F24 */
115	uint32_t VSI2_CTL; /* 0x80030F28 */
116	uint32_t VSI2_BS; /* 0x80030F2C */
117	uint32_t VSI2_BD; /* 0x80030F30 */
118	uint32_t VSI2_TO; /* 0x80030F34 */
119	uint32_t Buf_0x80030F38; /* 0x80030F38 */
120	uint32_t VSI3_CTL; /* 0x80030F3C */
121	uint32_t VSI3_BS; /* 0x80030F40 */
122	uint32_t VSI3_BD; /* 0x80030F44 */
123	uint32_t VSI3_TO; /* 0x80030F48 */
124	uint32_t Buf_0x80030F4C[ 0x9 ]; /* 0x80030F4C */
125	uint32_t VRAI_CTL; /* 0x80030F70 */
126	uint32_t VRAI_BS; /* 0x80030F74 */
127	uint32_t Buf_0x80030F78[ 0x2 ]; /* 0x80030F78 */
128	uint32_t VCSR_CTL; /* 0x80030F80 */
129	uint32_t VCSR_TO; /* 0x80030F84 */
130	uint32_t V_AMERR; /* 0x80030F88 */
131	uint32_t VAERR; /* 0x80030F8C */
132	uint32_t Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */
133	uint32_t VCSR_CLR; /* 0x80030FF4 */
134	uint32_t VCSR_SET; /* 0x80030FF8 */
135	uint32_t VCSR_BS; /* 0x80030FFC */
136	} Universe_Memory;
137
138	volatile Universe_Memory *UNIVERSE =
139	(volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE;
140
141
142	/********************************************************************
143	********************************************************************
144	******* *******
145	******* *******
146	******* *******
147	********************************************************************
148	********************************************************************/
149
150	/*
151	* Initializes the UNIVERSE chip. This routine is called automatically
152	* by the boot code. This routine should be called by user code only if
153	* a complete SCORE603e VME initialization is required.
154	*/
155
156	void initialize_universe()
157	{
158	uint32_t jumper_selection;
159	uint32_t pci_id;
160	#if (SCORE603E_USE_SDS) \| (SCORE603E_USE_OPEN_FIRMWARE) \| (SCORE603E_USE_NONE)
161	volatile uint32_t universe_temp_value;
162	#endif
163
164	/*
165	* Read the VME jumper location to determine the VME base address
166	*/
167	jumper_selection = PCI_bus_read(
168	(volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR );
169	jumper_selection = (jumper_selection >> 3) & 0x1f;
170
171	/*
172	* Verify the UNIVERSE CHIP ID
173	*/
174	pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE );
175
176	/*
177	* compare to known ID
178	*/
179	if (pci_id != SCORE603E_UNIVERSE_CHIP_ID ){
180	DEBUG_puts ("Invalid SCORE603E_UNIVERSE_CHIP_ID: ");
181	rtems_fatal_error_occurred( 0x603e0bad );
182	}
183
184	#if (SCORE603E_USE_SDS) \| (SCORE603E_USE_OPEN_FIRMWARE) \| (SCORE603E_USE_NONE)
185
186	/*
187	* Set the UNIVERSE PCI Configuration Base Address Register with 0x30001
188	* to specifies the 64 Kbyte aligned base address of the UNIVERSE register
189	* space on PCI to be 0x30000 + 0x80000000 (IO_BASE)
190	*/
191	Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 );
192
193	/*
194	* Set the UNIVERSE PCI Configuration Space Control and Status Register to
195	* medium speed device, Target Back to Back Capable, Master Enable, Target
196	* Memory Enable and Target IO Enable
197	*/
198	Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 );
199
200	/*
201	* Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
202	*/
203	PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
204
205	/*
206	* Set the VMEbus Master Control register with retry forever, 256 bytes
207	* posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
208	* aligned burst size and PCI bus number to be zero
209	*/
210	PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
211
212	/*
213	* VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
214	* width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
215	* single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
216	PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
217	*/
218
219	PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
220	PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 );
221	PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 );
222	PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 );
223
224	/*
225	* Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of
226	* BI-Mode VMEbus accesses can be made.
227	*/
228
229	universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
230
231	if (universe_temp_value & 0x100000)
232	PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value \| ~0xFF0FFFFF));
233
234	#elif (SCORE603E_USE_DINK)
235	/*
236	* Do not modify the DINK setup of the universe chip.
237	*/
238
239	#else
240	#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
241	#endif
242
243	}
244
245
246	/*
247	* Set the slave VME base address to the specified base address.
248	* Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
249	* Slave Image 0 registers.
250	*/
251	void set_vme_base_address (
252	uint32_t base_address
253	)
254	{
255	volatile uint32_t temp;
256
257	/*
258	* Calculate the current size of the Slave VME image 0
259	*/
260	temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
261	( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
262
263	/*
264	* Set the VMEbus Slave Image 0 Base Address to be
265	* the specifed base address on VSI0_BS register.
266	*/
267	PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
268
269	/*
270	* Update the VMEbus Slave Image 0 Bound Address.
271	*/
272	PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
273
274	/*
275	* Update the VMEbus Slave Image 0 Translation Offset
276	*/
277	temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
278	PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
279	}
280
281	/*
282	* Gets the VME base address
283	*/
284	uint32_t get_vme_base_address ()
285	{
286	volatile uint32_t temp;
287
288	temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
289	temp &= 0xFFFFF000;
290	return (temp);
291	}
292
293	uint32_t get_vme_slave_size()
294	{
295	volatile uint32_t temp;
296	temp = PCI_bus_read( &UNIVERSE->VSI0_BD);
297	temp &= 0xFFFFF000;
298	temp = temp - get_vme_base_address ();
299	return temp;
300	}
301
302	/*
303	* Set the size of the VME slave image
304	* Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
305	*/
306	void set_vme_slave_size (uint32_t size)
307	{
308	volatile uint32_t temp;
309
310	if (size<0)
311	size = 0;
312
313	if (size > 0x17FFFFF)
314	size = 0x17FFFFF;
315
316	/*
317	* Read the VME slave image base address
318	*/
319	temp = get_vme_base_address ();
320
321	/*
322	* Update the VMEbus Slave Image 0 Bound Address.
323	*/
324	temp = temp + (size & 0xFFFFF000);
325	PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
326	}
327

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