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source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c @ b00e693

4.104.114.84.95

Last change on this file since b00e693 was 50f93fb, checked in by Joel Sherrill <joel.sherrill@…>, on 09/17/07 at 14:09:43

2007-09-17 Joel Sherrill <joel.sherrill@…>

PCI_bus/universe.c, console/console.c, include/bsp.h, irq/FPGA.c, startup/bspstart.c, startup/genpvec.c, startup/spurious.c: Eliminate DEBUG_puts.

Property mode set to 100644

File size: 12.7 KB

Line
1	/*
2	*
3	* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
4	* On-Line Applications Research Corporation (OAR).
5	*
6	* $Id$
7	*/
8
9	#include <rtems.h>
10	#include <assert.h>
11	#include <stdio.h>
12	#include <inttypes.h>
13	#include <rtems/bspIo.h>
14
15	#include <bsp.h>
16	#include "PCI.h"
17
18	/********************************************************************
19	********************************************************************
20	******* *******
21	******* Prototypes *******
22	******* *******
23	********************************************************************
24	********************************************************************/
25
26	/********************************************************************
27	********************************************************************
28	******* *******
29	******* *******
30	******* *******
31	********************************************************************
32	********************************************************************/
33
34	typedef struct {
35	uint32_t PCI_ID; /* 0x80030000 */
36	uint32_t PCI_CSR; /* 0x80030004 */
37	uint32_t PCI_CLASS; /* 0x80030008 */
38	uint32_t PCI_MISC0; /* 0x8003000C */
39	uint32_t PCI_BS; /* 0x80030010 */
40	uint32_t Buf_0x80030014[ 0x0A ]; /* 0x80030014 */
41	uint32_t PCI_MISC1; /* 0x8003003C */
42	uint32_t Buf_0x80030040[ 0x30 ]; /* 0x80030040 */
43	uint32_t LSI0_CTL; /* 0x80030100 */
44	uint32_t LSI0_BS; /* 0x80030104 */
45	uint32_t LSI0_BD; /* 0x80030108 */
46	uint32_t LSI0_TO; /* 0x8003010C */
47	uint32_t Buf_0x80030110; /* 0x80030110 */
48	uint32_t LSI1_CTL; /* 0x80030114 */
49	uint32_t LSI1_BS; /* 0x80030118 */
50	uint32_t LSI1_BD; /* 0x8003011C */
51	uint32_t LSI1_TO; /* 0x80030120 */
52	uint32_t Buf_0x80030124; /* 0x80030124 */
53	uint32_t LSI2_CTL; /* 0x80030128 */
54	uint32_t LSI2_BS; /* 0x8003012C */
55	uint32_t LSI2_BD; /* 0x80030130 */
56	uint32_t LSI2_TO; /* 0x80030134 */
57	uint32_t Buf_0x80030138; /* 0x80030138 */
58	uint32_t LSI3_CTL; /* 0x8003013C */
59	uint32_t LSI3_BS; /* 0x80030140 */
60	uint32_t LSI3_BD; /* 0x80030144 */
61	uint32_t LSI3_TO; /* 0x80030148 */
62	uint32_t Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */
63	uint32_t SCYC_CTL; /* 0x80030170 */
64	uint32_t SCYC_ADDR; /* 0x80030174 */
65	uint32_t SCYC_EN; /* 0x80030178 */
66	uint32_t SCYC_CMP; /* 0x8003017C */
67	uint32_t SCYC_SWP; /* 0x80030180 */
68	uint32_t LMISC; /* 0x80030184 */
69	uint32_t SLSI; /* 0x80030188 */
70	uint32_t L_CMDERR; /* 0x8003018C */
71	uint32_t LAERR; /* 0x80030190 */
72	uint32_t Buf_0x80030194[ 0x1B ]; /* 0x80030194 */
73	uint32_t DCTL; /* 0x80030200 */
74	uint32_t DTBC; /* 0x80030204 */
75	uint32_t DLA; /* 0x80030208 */
76	uint32_t Buf_0x8003020C; /* 0x8003020C */
77	uint32_t DVA; /* 0x80030210 */
78	uint32_t Buf_0x80030214; /* 0x80030214 */
79	uint32_t DCPP; /* 0x80030218 */
80	uint32_t Buf_0x8003021C; /* 0x8003021C */
81	uint32_t DGCS; /* 0x80030220 */
82	uint32_t D_LLUE; /* 0x80030224 */
83	uint32_t Buf_0x80030228[ 0x36 ]; /* 0x80030228 */
84	uint32_t LINT_EN; /* 0x80030300 */
85	uint32_t LINT_STAT; /* 0x80030304 */
86	uint32_t LINT_MAP0; /* 0x80030308 */
87	uint32_t LINT_MAP1; /* 0x8003030C */
88	uint32_t VINT_EN; /* 0x80030310 */
89	uint32_t VINT_STAT; /* 0x80030314 */
90	uint32_t VINT_MAP0; /* 0x80030318 */
91	uint32_t VINT_MAP1; /* 0x8003031C */
92	uint32_t STATID; /* 0x80030320 */
93	uint32_t V1_STATID; /* 0x80030324 */
94	uint32_t V2_STATID; /* 0x80030328 */
95	uint32_t V3_STATID; /* 0x8003032C */
96	uint32_t V4_STATID; /* 0x80030330 */
97	uint32_t V5_STATID; /* 0x80030334 */
98	uint32_t V6_STATID; /* 0x80030338 */
99	uint32_t V7_STATID; /* 0x8003033C */
100	uint32_t Buf_0x80030340[ 0x30 ]; /* 0x80030340 */
101	uint32_t MAST_CTL; /* 0x80030400 */
102	uint32_t MISC_CTL; /* 0x80030404 */
103	uint32_t MISC_STAT; /* 0x80030408 */
104	uint32_t USER_AM; /* 0x8003040C */
105	uint32_t Buf_0x80030410[ 0x2bc ];/* 0x80030410 */
106	uint32_t VSI0_CTL; /* 0x80030F00 */
107	uint32_t VSI0_BS; /* 0x80030F04 */
108	uint32_t VSI0_BD; /* 0x80030F08 */
109	uint32_t VSI0_TO; /* 0x80030F0C */
110	uint32_t Buf_0x80030f10; /* 0x80030F10 */
111	uint32_t VSI1_CTL; /* 0x80030F14 */
112	uint32_t VSI1_BS; /* 0x80030F18 */
113	uint32_t VSI1_BD; /* 0x80030F1C */
114	uint32_t VSI1_TO; /* 0x80030F20 */
115	uint32_t Buf_0x80030F24; /* 0x80030F24 */
116	uint32_t VSI2_CTL; /* 0x80030F28 */
117	uint32_t VSI2_BS; /* 0x80030F2C */
118	uint32_t VSI2_BD; /* 0x80030F30 */
119	uint32_t VSI2_TO; /* 0x80030F34 */
120	uint32_t Buf_0x80030F38; /* 0x80030F38 */
121	uint32_t VSI3_CTL; /* 0x80030F3C */
122	uint32_t VSI3_BS; /* 0x80030F40 */
123	uint32_t VSI3_BD; /* 0x80030F44 */
124	uint32_t VSI3_TO; /* 0x80030F48 */
125	uint32_t Buf_0x80030F4C[ 0x9 ]; /* 0x80030F4C */
126	uint32_t VRAI_CTL; /* 0x80030F70 */
127	uint32_t VRAI_BS; /* 0x80030F74 */
128	uint32_t Buf_0x80030F78[ 0x2 ]; /* 0x80030F78 */
129	uint32_t VCSR_CTL; /* 0x80030F80 */
130	uint32_t VCSR_TO; /* 0x80030F84 */
131	uint32_t V_AMERR; /* 0x80030F88 */
132	uint32_t VAERR; /* 0x80030F8C */
133	uint32_t Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */
134	uint32_t VCSR_CLR; /* 0x80030FF4 */
135	uint32_t VCSR_SET; /* 0x80030FF8 */
136	uint32_t VCSR_BS; /* 0x80030FFC */
137	} Universe_Memory;
138
139	volatile Universe_Memory *UNIVERSE =
140	(volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE;
141
142	/********************************************************************
143	********************************************************************
144	******* *******
145	******* *******
146	******* *******
147	********************************************************************
148	********************************************************************/
149
150	/*
151	* Initializes the UNIVERSE chip. This routine is called automatically
152	* by the boot code. This routine should be called by user code only if
153	* a complete SCORE603e VME initialization is required.
154	*/
155
156	void initialize_universe()
157	{
158	uint32_t jumper_selection;
159	uint32_t pci_id;
160	#if (SCORE603E_USE_SDS) \| (SCORE603E_USE_OPEN_FIRMWARE) \| (SCORE603E_USE_NONE)
161	volatile uint32_t universe_temp_value;
162	#endif
163
164	/*
165	* Read the VME jumper location to determine the VME base address
166	*/
167	jumper_selection = PCI_bus_read(
168	(volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR );
169	jumper_selection = (jumper_selection >> 3) & 0x1f;
170
171	/*
172	* Verify the UNIVERSE CHIP ID
173	*/
174	pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE );
175
176	/*
177	* compare to known ID
178	*/
179	if (pci_id != SCORE603E_UNIVERSE_CHIP_ID ){
180	printk ("Invalid SCORE603E_UNIVERSE_CHIP_ID: 0x08%" PRId32 "\n", pci_id);
181	rtems_fatal_error_occurred( 0x603e0bad );
182	}
183
184	#if (SCORE603E_USE_SDS) \| (SCORE603E_USE_OPEN_FIRMWARE) \| (SCORE603E_USE_NONE)
185
186	/*
187	* Set the UNIVERSE PCI Configuration Base Address Register with 0x30001
188	* to specifies the 64 Kbyte aligned base address of the UNIVERSE register
189	* space on PCI to be 0x30000 + 0x80000000 (IO_BASE)
190	*/
191	Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 );
192
193	/*
194	* Set the UNIVERSE PCI Configuration Space Control and Status Register to
195	* medium speed device, Target Back to Back Capable, Master Enable, Target
196	* Memory Enable and Target IO Enable
197	*/
198	Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 );
199
200	/*
201	* Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
202	*/
203	PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
204
205	/*
206	* Set the VMEbus Master Control register with retry forever, 256 bytes
207	* posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
208	* aligned burst size and PCI bus number to be zero
209	*/
210	PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
211
212	/*
213	* VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
214	* width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
215	* single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
216	PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
217	*/
218
219	PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
220	PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 );
221	PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 );
222	PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 );
223
224	/*
225	* Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of
226	* BI-Mode VMEbus accesses can be made.
227	*/
228
229	universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
230
231	if (universe_temp_value & 0x100000)
232	PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value \| ~0xFF0FFFFF));
233
234	#elif (SCORE603E_USE_DINK)
235	/*
236	* Do not modify the DINK setup of the universe chip.
237	*/
238
239	#else
240	#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
241	#endif
242
243	}
244
245	/*
246	* Set the slave VME base address to the specified base address.
247	* Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
248	* Slave Image 0 registers.
249	*/
250	void set_vme_base_address (
251	uint32_t base_address
252	)
253	{
254	volatile uint32_t temp;
255
256	/*
257	* Calculate the current size of the Slave VME image 0
258	*/
259	temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
260	( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
261
262	/*
263	* Set the VMEbus Slave Image 0 Base Address to be
264	* the specifed base address on VSI0_BS register.
265	*/
266	PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
267
268	/*
269	* Update the VMEbus Slave Image 0 Bound Address.
270	*/
271	PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
272
273	/*
274	* Update the VMEbus Slave Image 0 Translation Offset
275	*/
276	temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
277	PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
278	}
279
280	/*
281	* Gets the VME base address
282	*/
283	uint32_t get_vme_base_address ()
284	{
285	volatile uint32_t temp;
286
287	temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
288	temp &= 0xFFFFF000;
289	return (temp);
290	}
291
292	uint32_t get_vme_slave_size()
293	{
294	volatile uint32_t temp;
295	temp = PCI_bus_read( &UNIVERSE->VSI0_BD);
296	temp &= 0xFFFFF000;
297	temp = temp - get_vme_base_address ();
298	return temp;
299	}
300
301	/*
302	* Set the size of the VME slave image
303	* Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
304	*/
305	void set_vme_slave_size (uint32_t size)
306	{
307	volatile uint32_t temp;
308
309	if (size<0)
310	size = 0;
311
312	if (size > 0x17FFFFF)
313	size = 0x17FFFFF;
314
315	/*
316	* Read the VME slave image base address
317	*/
318	temp = get_vme_base_address ();
319
320	/*
321	* Update the VMEbus Slave Image 0 Bound Address.
322	*/
323	temp = temp + (size & 0xFFFFF000);
324	PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
325	}

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