source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c @ 9c448e1

4.104.114.84.95
Last change on this file since 9c448e1 was 9c448e1, checked in by Joel Sherrill <joel.sherrill@…>, on 02/19/99 at 00:22:33

BSP for Vista Score603e added.
  • Property mode set to 100644
File size: 12.9 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
4 *  On-Line Applications Research Corporation (OAR).
5 *  All rights assigned to U.S. Government, 1994.
6 *
7 *  This material may be reproduced by or for the U.S. Government pursuant
8 *  to the copyright license under the clause at DFARS 252.227-7013.  This
9 *  notice must appear in all copies of this file and its derivatives.
10 *
11 * $ld:
12 */
13
14#include <rtems.h>
15#include <assert.h>
16#include <stdio.h>
17
18#include <bsp.h>
19#include "PCI.h"
20
21/********************************************************************
22 ********************************************************************
23 *********                                                  *********
24 *********                  Prototypes                      *********
25 *********                                                  *********
26 ********************************************************************
27 ********************************************************************/
28
29
30/********************************************************************
31 ********************************************************************
32 *********                                                  *********
33 *********                                                  *********
34 *********                                                  *********
35 ********************************************************************
36 ********************************************************************/
37
38typedef struct {
39  rtems_unsigned32 PCI_ID;                 /* 0x80030000 */
40  rtems_unsigned32 PCI_CSR;                /* 0x80030004 */
41  rtems_unsigned32 PCI_CLASS;              /* 0x80030008 */
42  rtems_unsigned32 PCI_MISC0;              /* 0x8003000C */
43  rtems_unsigned32 PCI_BS;                 /* 0x80030010 */
44  rtems_unsigned32 Buf_0x80030014[ 0x0A ]; /* 0x80030014 */
45  rtems_unsigned32 PCI_MISC1;              /* 0x8003003C */
46  rtems_unsigned32 Buf_0x80030040[ 0x30 ]; /* 0x80030040 */
47  rtems_unsigned32 LSI0_CTL;               /* 0x80030100 */
48  rtems_unsigned32 LSI0_BS;                /* 0x80030104 */
49  rtems_unsigned32 LSI0_BD;                /* 0x80030108 */
50  rtems_unsigned32 LSI0_TO;                /* 0x8003010C */
51  rtems_unsigned32 Buf_0x80030110;         /* 0x80030110 */
52  rtems_unsigned32 LSI1_CTL;               /* 0x80030114 */
53  rtems_unsigned32 LSI1_BS;                /* 0x80030118 */
54  rtems_unsigned32 LSI1_BD;                /* 0x8003011C */
55  rtems_unsigned32 LSI1_TO;                /* 0x80030120 */
56  rtems_unsigned32 Buf_0x80030124;         /* 0x80030124 */
57  rtems_unsigned32 LSI2_CTL;               /* 0x80030128 */
58  rtems_unsigned32 LSI2_BS;                /* 0x8003012C */
59  rtems_unsigned32 LSI2_BD;                /* 0x80030130 */
60  rtems_unsigned32 LSI2_TO;                /* 0x80030134 */
61  rtems_unsigned32 Buf_0x80030138;         /* 0x80030138 */
62  rtems_unsigned32 LSI3_CTL;               /* 0x8003013C */
63  rtems_unsigned32 LSI3_BS;                /* 0x80030140 */
64  rtems_unsigned32 LSI3_BD;                /* 0x80030144 */
65  rtems_unsigned32 LSI3_TO;                /* 0x80030148 */
66  rtems_unsigned32 Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */
67  rtems_unsigned32 SCYC_CTL;               /* 0x80030170 */
68  rtems_unsigned32 SCYC_ADDR;              /* 0x80030174 */
69  rtems_unsigned32 SCYC_EN;                /* 0x80030178 */
70  rtems_unsigned32 SCYC_CMP;               /* 0x8003017C */
71  rtems_unsigned32 SCYC_SWP;               /* 0x80030180 */
72  rtems_unsigned32 LMISC;                  /* 0x80030184 */
73  rtems_unsigned32 SLSI;                   /* 0x80030188 */
74  rtems_unsigned32 L_CMDERR;               /* 0x8003018C */
75  rtems_unsigned32 LAERR;                  /* 0x80030190 */
76  rtems_unsigned32 Buf_0x80030194[ 0x1B ]; /* 0x80030194 */
77  rtems_unsigned32 DCTL;                   /* 0x80030200 */
78  rtems_unsigned32 DTBC;                   /* 0x80030204 */
79  rtems_unsigned32 DLA;                    /* 0x80030208 */
80  rtems_unsigned32 Buf_0x8003020C;         /* 0x8003020C */
81  rtems_unsigned32 DVA;                    /* 0x80030210 */
82  rtems_unsigned32 Buf_0x80030214;         /* 0x80030214 */
83  rtems_unsigned32 DCPP;                   /* 0x80030218 */
84  rtems_unsigned32 Buf_0x8003021C;         /* 0x8003021C */
85  rtems_unsigned32 DGCS;                   /* 0x80030220 */
86  rtems_unsigned32 D_LLUE;                 /* 0x80030224 */
87  rtems_unsigned32 Buf_0x80030228[ 0x36 ]; /* 0x80030228 */
88  rtems_unsigned32 LINT_EN;                /* 0x80030300 */
89  rtems_unsigned32 LINT_STAT;              /* 0x80030304 */
90  rtems_unsigned32 LINT_MAP0;              /* 0x80030308 */
91  rtems_unsigned32 LINT_MAP1;              /* 0x8003030C */
92  rtems_unsigned32 VINT_EN;                /* 0x80030310 */
93  rtems_unsigned32 VINT_STAT;              /* 0x80030314 */
94  rtems_unsigned32 VINT_MAP0;              /* 0x80030318 */
95  rtems_unsigned32 VINT_MAP1;              /* 0x8003031C */
96  rtems_unsigned32 STATID;                 /* 0x80030320 */
97  rtems_unsigned32 V1_STATID;              /* 0x80030324 */
98  rtems_unsigned32 V2_STATID;              /* 0x80030328 */
99  rtems_unsigned32 V3_STATID;              /* 0x8003032C */
100  rtems_unsigned32 V4_STATID;              /* 0x80030330 */
101  rtems_unsigned32 V5_STATID;              /* 0x80030334 */
102  rtems_unsigned32 V6_STATID;              /* 0x80030338 */
103  rtems_unsigned32 V7_STATID;              /* 0x8003033C */
104  rtems_unsigned32 Buf_0x80030340[ 0x30 ]; /* 0x80030340 */
105  rtems_unsigned32 MAST_CTL;               /* 0x80030400 */
106  rtems_unsigned32 MISC_CTL;               /* 0x80030404 */
107  rtems_unsigned32 MISC_STAT;              /* 0x80030408 */
108  rtems_unsigned32 USER_AM;                /* 0x8003040C */
109  rtems_unsigned32 Buf_0x80030410[ 0x2bc ];/* 0x80030410 */
110  rtems_unsigned32 VSI0_CTL;               /* 0x80030F00 */
111  rtems_unsigned32 VSI0_BS;                /* 0x80030F04 */
112  rtems_unsigned32 VSI0_BD;                /* 0x80030F08 */
113  rtems_unsigned32 VSI0_TO;                /* 0x80030F0C */
114  rtems_unsigned32 Buf_0x80030f10;         /* 0x80030F10 */
115  rtems_unsigned32 VSI1_CTL;               /* 0x80030F14 */
116  rtems_unsigned32 VSI1_BS;                /* 0x80030F18 */
117  rtems_unsigned32 VSI1_BD;                /* 0x80030F1C */
118  rtems_unsigned32 VSI1_TO;                /* 0x80030F20 */
119  rtems_unsigned32 Buf_0x80030F24;         /* 0x80030F24 */
120  rtems_unsigned32 VSI2_CTL;               /* 0x80030F28 */
121  rtems_unsigned32 VSI2_BS;                /* 0x80030F2C */
122  rtems_unsigned32 VSI2_BD;                /* 0x80030F30 */
123  rtems_unsigned32 VSI2_TO;                /* 0x80030F34 */
124  rtems_unsigned32 Buf_0x80030F38;         /* 0x80030F38 */
125  rtems_unsigned32 VSI3_CTL;               /* 0x80030F3C */
126  rtems_unsigned32 VSI3_BS;                /* 0x80030F40 */
127  rtems_unsigned32 VSI3_BD;                /* 0x80030F44 */
128  rtems_unsigned32 VSI3_TO;                /* 0x80030F48 */
129  rtems_unsigned32 Buf_0x80030F4C[ 0x9 ];  /* 0x80030F4C */
130  rtems_unsigned32 VRAI_CTL;               /* 0x80030F70 */
131  rtems_unsigned32 VRAI_BS;                /* 0x80030F74 */
132  rtems_unsigned32 Buf_0x80030F78[ 0x2 ];  /* 0x80030F78 */
133  rtems_unsigned32 VCSR_CTL;               /* 0x80030F80 */
134  rtems_unsigned32 VCSR_TO;                /* 0x80030F84 */
135  rtems_unsigned32 V_AMERR;                /* 0x80030F88 */
136  rtems_unsigned32 VAERR;                  /* 0x80030F8C */
137  rtems_unsigned32 Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */
138  rtems_unsigned32 VCSR_CLR;               /* 0x80030FF4 */
139  rtems_unsigned32 VCSR_SET;               /* 0x80030FF8 */
140  rtems_unsigned32 VCSR_BS;                /* 0x80030FFC */
141} Universe_Memory;
142
143volatile Universe_Memory *UNIVERSE =
144                         (volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE;
145
146
147/********************************************************************
148 ********************************************************************
149 *********                                                  *********
150 *********                                                  *********
151 *********                                                  *********
152 ********************************************************************
153 ********************************************************************/
154
155/*
156 * Initializes the UNIVERSE chip.  This routine is called automatically
157 * by the boot code.  This routine should be called by user code only if
158 * a complete SCORE603e VME initialization is required.
159 */
160
161void initialize_universe()
162{
163  rtems_unsigned32 jumper_selection;
164  rtems_unsigned32 pci_id;
165  volatile rtems_unsigned32 universe_temp_value;
166 
167  /*
168   * Read the VME jumper location to determine the VME base address
169   */
170  jumper_selection = PCI_bus_read(
171                     (volatile rtems_unsigned32 *)SCORE603E_VME_JUMPER_ADDR );
172  jumper_selection = (jumper_selection >> 3) & 0x1f;
173
174  /*
175   * Verify the UNIVERSE CHIP ID
176   */
177   pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE );
178
179   /*
180    * compare to known ID
181    */
182   if (pci_id !=  SCORE603E_UNIVERSE_CHIP_ID ){
183     DEBUG_puts ("Invalid SCORE603E_UNIVERSE_CHIP_ID: ");
184     rtems_fatal_error_occurred( 0x603e0bad );
185   }
186
187#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
188
189   /*
190    * Set the UNIVERSE PCI Configuration Base Address Register with 0x30001
191    * to specifies the 64 Kbyte aligned base address of the UNIVERSE register
192    * space on PCI to be 0x30000 + 0x80000000 (IO_BASE)
193    */
194   Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 );
195
196   /*
197    * Set the UNIVERSE PCI Configuration Space Control and Status Register to
198    * medium speed device, Target Back to Back Capable, Master Enable, Target
199    * Memory Enable and Target IO Enable
200    */
201   Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 );
202
203   /*
204    * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
205    */
206   PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );   
207
208   /*
209    * Set the VMEbus Master Control register with retry forever, 256 bytes
210    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
211    * aligned burst size and PCI bus number to be zero
212    */
213   PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
214
215   /*
216    * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
217    * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
218    * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
219    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );   
220    */
221   
222   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
223   PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
224   PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
225   PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );
226
227   /*
228    * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
229    * BI-Mode VMEbus accesses can be made.
230    */
231
232   universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
233
234   if (universe_temp_value & 0x100000)
235     PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
236
237#elif (SCORE603E_USE_DINK)
238   /*
239    * Do not modify the DINK setup of the universe chip.
240    */
241
242#else
243#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
244#endif
245
246}
247
248
249/*
250 * Set the slave VME base address to the specified base address.
251 * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
252 *       Slave Image 0 registers.
253 */
254void set_vme_base_address (
255  rtems_unsigned32 base_address
256)
257{ 
258  volatile rtems_unsigned32 temp;
259
260  /*
261   * Calculate the current size of the Slave VME image 0
262   */
263  temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
264          ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
265
266  /*
267   * Set the VMEbus Slave Image 0 Base Address to be
268   * the specifed base address on VSI0_BS register.
269   */
270   PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );   
271
272  /*
273   * Update the VMEbus Slave Image 0 Bound Address.
274   */
275  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
276
277  /*
278   * Update the VMEbus Slave Image 0 Translation Offset
279   */
280  temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
281  PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
282}
283
284/*
285 * Gets the VME base address
286 */
287rtems_unsigned32 get_vme_base_address ()
288{ 
289  volatile rtems_unsigned32 temp;
290
291  temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
292  temp &= 0xFFFFF000;
293  return (temp);
294}
295
296rtems_unsigned32 get_vme_slave_size()
297{
298  volatile rtems_unsigned32 temp;
299  temp  =  PCI_bus_read( &UNIVERSE->VSI0_BD);
300  temp &= 0xFFFFF000;
301  temp  = temp - get_vme_base_address ();
302  return temp;
303}
304
305/*
306 * Set the size of the VME slave image
307 * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
308 */
309void set_vme_slave_size (rtems_unsigned32 size)
310{ 
311  volatile rtems_unsigned32 temp;
312
313  if (size<0)
314    size = 0;
315 
316  if (size > 0x17FFFFF)
317    size = 0x17FFFFF;
318   
319  /*
320   * Read the VME slave image base address
321   */
322  temp = get_vme_base_address ();
323
324  /*
325   * Update the VMEbus Slave Image 0 Bound Address.
326   */
327  temp = temp + (size & 0xFFFFF000);
328  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
329}
330
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