1 | /* |
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2 | * |
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3 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997. |
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4 | * On-Line Applications Research Corporation (OAR). |
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5 | * |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #include <rtems.h> |
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10 | #include <assert.h> |
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11 | #include <stdio.h> |
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12 | |
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13 | #include <bsp.h> |
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14 | #include "PCI.h" |
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15 | |
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16 | /******************************************************************** |
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17 | ******************************************************************** |
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18 | ********* ********* |
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19 | ********* Prototypes ********* |
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20 | ********* ********* |
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21 | ******************************************************************** |
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22 | ********************************************************************/ |
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23 | |
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24 | |
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25 | /******************************************************************** |
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26 | ******************************************************************** |
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27 | ********* ********* |
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28 | ********* ********* |
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29 | ********* ********* |
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30 | ******************************************************************** |
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31 | ********************************************************************/ |
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32 | |
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33 | typedef struct { |
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34 | uint32_t PCI_ID; /* 0x80030000 */ |
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35 | uint32_t PCI_CSR; /* 0x80030004 */ |
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36 | uint32_t PCI_CLASS; /* 0x80030008 */ |
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37 | uint32_t PCI_MISC0; /* 0x8003000C */ |
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38 | uint32_t PCI_BS; /* 0x80030010 */ |
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39 | uint32_t Buf_0x80030014[ 0x0A ]; /* 0x80030014 */ |
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40 | uint32_t PCI_MISC1; /* 0x8003003C */ |
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41 | uint32_t Buf_0x80030040[ 0x30 ]; /* 0x80030040 */ |
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42 | uint32_t LSI0_CTL; /* 0x80030100 */ |
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43 | uint32_t LSI0_BS; /* 0x80030104 */ |
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44 | uint32_t LSI0_BD; /* 0x80030108 */ |
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45 | uint32_t LSI0_TO; /* 0x8003010C */ |
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46 | uint32_t Buf_0x80030110; /* 0x80030110 */ |
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47 | uint32_t LSI1_CTL; /* 0x80030114 */ |
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48 | uint32_t LSI1_BS; /* 0x80030118 */ |
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49 | uint32_t LSI1_BD; /* 0x8003011C */ |
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50 | uint32_t LSI1_TO; /* 0x80030120 */ |
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51 | uint32_t Buf_0x80030124; /* 0x80030124 */ |
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52 | uint32_t LSI2_CTL; /* 0x80030128 */ |
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53 | uint32_t LSI2_BS; /* 0x8003012C */ |
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54 | uint32_t LSI2_BD; /* 0x80030130 */ |
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55 | uint32_t LSI2_TO; /* 0x80030134 */ |
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56 | uint32_t Buf_0x80030138; /* 0x80030138 */ |
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57 | uint32_t LSI3_CTL; /* 0x8003013C */ |
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58 | uint32_t LSI3_BS; /* 0x80030140 */ |
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59 | uint32_t LSI3_BD; /* 0x80030144 */ |
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60 | uint32_t LSI3_TO; /* 0x80030148 */ |
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61 | uint32_t Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */ |
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62 | uint32_t SCYC_CTL; /* 0x80030170 */ |
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63 | uint32_t SCYC_ADDR; /* 0x80030174 */ |
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64 | uint32_t SCYC_EN; /* 0x80030178 */ |
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65 | uint32_t SCYC_CMP; /* 0x8003017C */ |
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66 | uint32_t SCYC_SWP; /* 0x80030180 */ |
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67 | uint32_t LMISC; /* 0x80030184 */ |
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68 | uint32_t SLSI; /* 0x80030188 */ |
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69 | uint32_t L_CMDERR; /* 0x8003018C */ |
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70 | uint32_t LAERR; /* 0x80030190 */ |
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71 | uint32_t Buf_0x80030194[ 0x1B ]; /* 0x80030194 */ |
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72 | uint32_t DCTL; /* 0x80030200 */ |
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73 | uint32_t DTBC; /* 0x80030204 */ |
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74 | uint32_t DLA; /* 0x80030208 */ |
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75 | uint32_t Buf_0x8003020C; /* 0x8003020C */ |
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76 | uint32_t DVA; /* 0x80030210 */ |
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77 | uint32_t Buf_0x80030214; /* 0x80030214 */ |
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78 | uint32_t DCPP; /* 0x80030218 */ |
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79 | uint32_t Buf_0x8003021C; /* 0x8003021C */ |
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80 | uint32_t DGCS; /* 0x80030220 */ |
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81 | uint32_t D_LLUE; /* 0x80030224 */ |
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82 | uint32_t Buf_0x80030228[ 0x36 ]; /* 0x80030228 */ |
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83 | uint32_t LINT_EN; /* 0x80030300 */ |
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84 | uint32_t LINT_STAT; /* 0x80030304 */ |
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85 | uint32_t LINT_MAP0; /* 0x80030308 */ |
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86 | uint32_t LINT_MAP1; /* 0x8003030C */ |
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87 | uint32_t VINT_EN; /* 0x80030310 */ |
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88 | uint32_t VINT_STAT; /* 0x80030314 */ |
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89 | uint32_t VINT_MAP0; /* 0x80030318 */ |
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90 | uint32_t VINT_MAP1; /* 0x8003031C */ |
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91 | uint32_t STATID; /* 0x80030320 */ |
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92 | uint32_t V1_STATID; /* 0x80030324 */ |
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93 | uint32_t V2_STATID; /* 0x80030328 */ |
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94 | uint32_t V3_STATID; /* 0x8003032C */ |
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95 | uint32_t V4_STATID; /* 0x80030330 */ |
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96 | uint32_t V5_STATID; /* 0x80030334 */ |
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97 | uint32_t V6_STATID; /* 0x80030338 */ |
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98 | uint32_t V7_STATID; /* 0x8003033C */ |
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99 | uint32_t Buf_0x80030340[ 0x30 ]; /* 0x80030340 */ |
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100 | uint32_t MAST_CTL; /* 0x80030400 */ |
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101 | uint32_t MISC_CTL; /* 0x80030404 */ |
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102 | uint32_t MISC_STAT; /* 0x80030408 */ |
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103 | uint32_t USER_AM; /* 0x8003040C */ |
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104 | uint32_t Buf_0x80030410[ 0x2bc ];/* 0x80030410 */ |
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105 | uint32_t VSI0_CTL; /* 0x80030F00 */ |
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106 | uint32_t VSI0_BS; /* 0x80030F04 */ |
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107 | uint32_t VSI0_BD; /* 0x80030F08 */ |
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108 | uint32_t VSI0_TO; /* 0x80030F0C */ |
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109 | uint32_t Buf_0x80030f10; /* 0x80030F10 */ |
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110 | uint32_t VSI1_CTL; /* 0x80030F14 */ |
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111 | uint32_t VSI1_BS; /* 0x80030F18 */ |
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112 | uint32_t VSI1_BD; /* 0x80030F1C */ |
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113 | uint32_t VSI1_TO; /* 0x80030F20 */ |
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114 | uint32_t Buf_0x80030F24; /* 0x80030F24 */ |
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115 | uint32_t VSI2_CTL; /* 0x80030F28 */ |
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116 | uint32_t VSI2_BS; /* 0x80030F2C */ |
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117 | uint32_t VSI2_BD; /* 0x80030F30 */ |
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118 | uint32_t VSI2_TO; /* 0x80030F34 */ |
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119 | uint32_t Buf_0x80030F38; /* 0x80030F38 */ |
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120 | uint32_t VSI3_CTL; /* 0x80030F3C */ |
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121 | uint32_t VSI3_BS; /* 0x80030F40 */ |
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122 | uint32_t VSI3_BD; /* 0x80030F44 */ |
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123 | uint32_t VSI3_TO; /* 0x80030F48 */ |
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124 | uint32_t Buf_0x80030F4C[ 0x9 ]; /* 0x80030F4C */ |
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125 | uint32_t VRAI_CTL; /* 0x80030F70 */ |
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126 | uint32_t VRAI_BS; /* 0x80030F74 */ |
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127 | uint32_t Buf_0x80030F78[ 0x2 ]; /* 0x80030F78 */ |
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128 | uint32_t VCSR_CTL; /* 0x80030F80 */ |
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129 | uint32_t VCSR_TO; /* 0x80030F84 */ |
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130 | uint32_t V_AMERR; /* 0x80030F88 */ |
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131 | uint32_t VAERR; /* 0x80030F8C */ |
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132 | uint32_t Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */ |
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133 | uint32_t VCSR_CLR; /* 0x80030FF4 */ |
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134 | uint32_t VCSR_SET; /* 0x80030FF8 */ |
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135 | uint32_t VCSR_BS; /* 0x80030FFC */ |
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136 | } Universe_Memory; |
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137 | |
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138 | volatile Universe_Memory *UNIVERSE = |
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139 | (volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE; |
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140 | |
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141 | |
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142 | /******************************************************************** |
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143 | ******************************************************************** |
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144 | ********* ********* |
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145 | ********* ********* |
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146 | ********* ********* |
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147 | ******************************************************************** |
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148 | ********************************************************************/ |
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149 | |
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150 | /* |
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151 | * Initializes the UNIVERSE chip. This routine is called automatically |
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152 | * by the boot code. This routine should be called by user code only if |
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153 | * a complete SCORE603e VME initialization is required. |
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154 | */ |
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155 | |
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156 | void initialize_universe() |
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157 | { |
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158 | uint32_t jumper_selection; |
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159 | uint32_t pci_id; |
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160 | #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) |
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161 | volatile uint32_t universe_temp_value; |
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162 | #endif |
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163 | |
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164 | /* |
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165 | * Read the VME jumper location to determine the VME base address |
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166 | */ |
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167 | jumper_selection = PCI_bus_read( |
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168 | (volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR ); |
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169 | jumper_selection = (jumper_selection >> 3) & 0x1f; |
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170 | |
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171 | /* |
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172 | * Verify the UNIVERSE CHIP ID |
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173 | */ |
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174 | pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE ); |
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175 | |
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176 | /* |
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177 | * compare to known ID |
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178 | */ |
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179 | if (pci_id != SCORE603E_UNIVERSE_CHIP_ID ){ |
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180 | DEBUG_puts ("Invalid SCORE603E_UNIVERSE_CHIP_ID: "); |
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181 | rtems_fatal_error_occurred( 0x603e0bad ); |
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182 | } |
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183 | |
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184 | #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) |
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185 | |
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186 | /* |
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187 | * Set the UNIVERSE PCI Configuration Base Address Register with 0x30001 |
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188 | * to specifies the 64 Kbyte aligned base address of the UNIVERSE register |
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189 | * space on PCI to be 0x30000 + 0x80000000 (IO_BASE) |
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190 | */ |
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191 | Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 ); |
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192 | |
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193 | /* |
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194 | * Set the UNIVERSE PCI Configuration Space Control and Status Register to |
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195 | * medium speed device, Target Back to Back Capable, Master Enable, Target |
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196 | * Memory Enable and Target IO Enable |
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197 | */ |
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198 | Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 ); |
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199 | |
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200 | /* |
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201 | * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register |
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202 | */ |
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203 | PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 ); |
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204 | |
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205 | /* |
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206 | * Set the VMEbus Master Control register with retry forever, 256 bytes |
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207 | * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes |
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208 | * aligned burst size and PCI bus number to be zero |
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209 | */ |
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210 | PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 ); |
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211 | |
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212 | /* |
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213 | * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data |
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214 | * width, A32 VMEbus Address Space, AM code to be data, none-privilleged, |
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215 | * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable |
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216 | PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 ); |
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217 | */ |
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218 | |
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219 | PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); |
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220 | PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 ); |
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221 | PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 ); |
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222 | PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 ); |
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223 | |
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224 | /* |
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225 | * Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of |
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226 | * BI-Mode VMEbus accesses can be made. |
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227 | */ |
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228 | |
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229 | universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL ); |
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230 | |
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231 | if (universe_temp_value & 0x100000) |
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232 | PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF)); |
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233 | |
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234 | #elif (SCORE603E_USE_DINK) |
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235 | /* |
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236 | * Do not modify the DINK setup of the universe chip. |
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237 | */ |
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238 | |
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239 | #else |
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240 | #error "SCORE603E BSPSTART.C -- what ROM monitor are you using" |
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241 | #endif |
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242 | |
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243 | } |
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244 | |
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245 | |
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246 | /* |
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247 | * Set the slave VME base address to the specified base address. |
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248 | * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus |
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249 | * Slave Image 0 registers. |
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250 | */ |
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251 | void set_vme_base_address ( |
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252 | uint32_t base_address |
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253 | ) |
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254 | { |
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255 | volatile uint32_t temp; |
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256 | |
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257 | /* |
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258 | * Calculate the current size of the Slave VME image 0 |
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259 | */ |
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260 | temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - |
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261 | ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000); |
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262 | |
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263 | /* |
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264 | * Set the VMEbus Slave Image 0 Base Address to be |
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265 | * the specifed base address on VSI0_BS register. |
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266 | */ |
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267 | PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) ); |
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268 | |
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269 | /* |
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270 | * Update the VMEbus Slave Image 0 Bound Address. |
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271 | */ |
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272 | PCI_bus_write( &UNIVERSE->VSI0_BD, temp ); |
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273 | |
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274 | /* |
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275 | * Update the VMEbus Slave Image 0 Translation Offset |
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276 | */ |
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277 | temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000; |
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278 | PCI_bus_write( &UNIVERSE->VSI0_TO, temp ); |
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279 | } |
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280 | |
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281 | /* |
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282 | * Gets the VME base address |
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283 | */ |
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284 | uint32_t get_vme_base_address () |
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285 | { |
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286 | volatile uint32_t temp; |
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287 | |
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288 | temp = PCI_bus_read( &UNIVERSE->VSI0_BS ); |
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289 | temp &= 0xFFFFF000; |
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290 | return (temp); |
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291 | } |
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292 | |
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293 | uint32_t get_vme_slave_size() |
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294 | { |
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295 | volatile uint32_t temp; |
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296 | temp = PCI_bus_read( &UNIVERSE->VSI0_BD); |
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297 | temp &= 0xFFFFF000; |
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298 | temp = temp - get_vme_base_address (); |
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299 | return temp; |
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300 | } |
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301 | |
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302 | /* |
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303 | * Set the size of the VME slave image |
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304 | * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) |
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305 | */ |
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306 | void set_vme_slave_size (uint32_t size) |
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307 | { |
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308 | volatile uint32_t temp; |
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309 | |
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310 | if (size<0) |
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311 | size = 0; |
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312 | |
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313 | if (size > 0x17FFFFF) |
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314 | size = 0x17FFFFF; |
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315 | |
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316 | /* |
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317 | * Read the VME slave image base address |
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318 | */ |
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319 | temp = get_vme_base_address (); |
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320 | |
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321 | /* |
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322 | * Update the VMEbus Slave Image 0 Bound Address. |
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323 | */ |
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324 | temp = temp + (size & 0xFFFFF000); |
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325 | PCI_bus_write( &UNIVERSE->VSI0_BD, temp ); |
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326 | } |
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