Context Navigation

universe.c @ 31a5ec8

4.9

Last change on this file since 31a5ec8 was 31a5ec8, checked in by Jennifer Averett <Jennifer.Averett@…>, on 05/05/09 at 16:18:06

2009-05-05 Jennifer Averett <jennifer.averett@…>

Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with the latest powerpc isr source
irq/no_pic.c: New file.
irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.

Property mode set to 100644

File size: 10.9 KB

Line
1	/*
2	* COPYRIGHT (c) 1989-2009.
3	* On-Line Applications Research Corporation (OAR).
4	*
5	* The license and distribution terms for this file may be
6	* found in the file LICENSE in this distribution or at
7	* http://www.rtems.com/license/LICENSE.
8	*
9	* $Id$
10	*/
11
12	#include <rtems.h>
13	#include <assert.h>
14	#include <stdio.h>
15	#include <inttypes.h>
16	#include <rtems/bspIo.h>
17
18	#include <bsp.h>
19	#include "PCI.h"
20
21	/********************************************************************
22	********************************************************************
23	******* *******
24	******* Prototypes *******
25	******* *******
26	********************************************************************
27	********************************************************************/
28
29	/********************************************************************
30	********************************************************************
31	******* *******
32	******* *******
33	******* *******
34	********************************************************************
35	********************************************************************/
36
37	typedef struct {
38	uint32_t PCI_ID; /* 0x80030000 */
39	uint32_t PCI_CSR; /* 0x80030004 */
40	uint32_t PCI_CLASS; /* 0x80030008 */
41	uint32_t PCI_MISC0; /* 0x8003000C */
42	uint32_t PCI_BS; /* 0x80030010 */
43	uint32_t Buf_0x80030014[ 0x0A ]; /* 0x80030014 */
44	uint32_t PCI_MISC1; /* 0x8003003C */
45	uint32_t Buf_0x80030040[ 0x30 ]; /* 0x80030040 */
46	uint32_t LSI0_CTL; /* 0x80030100 */
47	uint32_t LSI0_BS; /* 0x80030104 */
48	uint32_t LSI0_BD; /* 0x80030108 */
49	uint32_t LSI0_TO; /* 0x8003010C */
50	uint32_t Buf_0x80030110; /* 0x80030110 */
51	uint32_t LSI1_CTL; /* 0x80030114 */
52	uint32_t LSI1_BS; /* 0x80030118 */
53	uint32_t LSI1_BD; /* 0x8003011C */
54	uint32_t LSI1_TO; /* 0x80030120 */
55	uint32_t Buf_0x80030124; /* 0x80030124 */
56	uint32_t LSI2_CTL; /* 0x80030128 */
57	uint32_t LSI2_BS; /* 0x8003012C */
58	uint32_t LSI2_BD; /* 0x80030130 */
59	uint32_t LSI2_TO; /* 0x80030134 */
60	uint32_t Buf_0x80030138; /* 0x80030138 */
61	uint32_t LSI3_CTL; /* 0x8003013C */
62	uint32_t LSI3_BS; /* 0x80030140 */
63	uint32_t LSI3_BD; /* 0x80030144 */
64	uint32_t LSI3_TO; /* 0x80030148 */
65	uint32_t Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */
66	uint32_t SCYC_CTL; /* 0x80030170 */
67	uint32_t SCYC_ADDR; /* 0x80030174 */
68	uint32_t SCYC_EN; /* 0x80030178 */
69	uint32_t SCYC_CMP; /* 0x8003017C */
70	uint32_t SCYC_SWP; /* 0x80030180 */
71	uint32_t LMISC; /* 0x80030184 */
72	uint32_t SLSI; /* 0x80030188 */
73	uint32_t L_CMDERR; /* 0x8003018C */
74	uint32_t LAERR; /* 0x80030190 */
75	uint32_t Buf_0x80030194[ 0x1B ]; /* 0x80030194 */
76	uint32_t DCTL; /* 0x80030200 */
77	uint32_t DTBC; /* 0x80030204 */
78	uint32_t DLA; /* 0x80030208 */
79	uint32_t Buf_0x8003020C; /* 0x8003020C */
80	uint32_t DVA; /* 0x80030210 */
81	uint32_t Buf_0x80030214; /* 0x80030214 */
82	uint32_t DCPP; /* 0x80030218 */
83	uint32_t Buf_0x8003021C; /* 0x8003021C */
84	uint32_t DGCS; /* 0x80030220 */
85	uint32_t D_LLUE; /* 0x80030224 */
86	uint32_t Buf_0x80030228[ 0x36 ]; /* 0x80030228 */
87	uint32_t LINT_EN; /* 0x80030300 */
88	uint32_t LINT_STAT; /* 0x80030304 */
89	uint32_t LINT_MAP0; /* 0x80030308 */
90	uint32_t LINT_MAP1; /* 0x8003030C */
91	uint32_t VINT_EN; /* 0x80030310 */
92	uint32_t VINT_STAT; /* 0x80030314 */
93	uint32_t VINT_MAP0; /* 0x80030318 */
94	uint32_t VINT_MAP1; /* 0x8003031C */
95	uint32_t STATID; /* 0x80030320 */
96	uint32_t V1_STATID; /* 0x80030324 */
97	uint32_t V2_STATID; /* 0x80030328 */
98	uint32_t V3_STATID; /* 0x8003032C */
99	uint32_t V4_STATID; /* 0x80030330 */
100	uint32_t V5_STATID; /* 0x80030334 */
101	uint32_t V6_STATID; /* 0x80030338 */
102	uint32_t V7_STATID; /* 0x8003033C */
103	uint32_t Buf_0x80030340[ 0x30 ]; /* 0x80030340 */
104	uint32_t MAST_CTL; /* 0x80030400 */
105	uint32_t MISC_CTL; /* 0x80030404 */
106	uint32_t MISC_STAT; /* 0x80030408 */
107	uint32_t USER_AM; /* 0x8003040C */
108	uint32_t Buf_0x80030410[ 0x2bc ];/* 0x80030410 */
109	uint32_t VSI0_CTL; /* 0x80030F00 */
110	uint32_t VSI0_BS; /* 0x80030F04 */
111	uint32_t VSI0_BD; /* 0x80030F08 */
112	uint32_t VSI0_TO; /* 0x80030F0C */
113	uint32_t Buf_0x80030f10; /* 0x80030F10 */
114	uint32_t VSI1_CTL; /* 0x80030F14 */
115	uint32_t VSI1_BS; /* 0x80030F18 */
116	uint32_t VSI1_BD; /* 0x80030F1C */
117	uint32_t VSI1_TO; /* 0x80030F20 */
118	uint32_t Buf_0x80030F24; /* 0x80030F24 */
119	uint32_t VSI2_CTL; /* 0x80030F28 */
120	uint32_t VSI2_BS; /* 0x80030F2C */
121	uint32_t VSI2_BD; /* 0x80030F30 */
122	uint32_t VSI2_TO; /* 0x80030F34 */
123	uint32_t Buf_0x80030F38; /* 0x80030F38 */
124	uint32_t VSI3_CTL; /* 0x80030F3C */
125	uint32_t VSI3_BS; /* 0x80030F40 */
126	uint32_t VSI3_BD; /* 0x80030F44 */
127	uint32_t VSI3_TO; /* 0x80030F48 */
128	uint32_t Buf_0x80030F4C[ 0x9 ]; /* 0x80030F4C */
129	uint32_t VRAI_CTL; /* 0x80030F70 */
130	uint32_t VRAI_BS; /* 0x80030F74 */
131	uint32_t Buf_0x80030F78[ 0x2 ]; /* 0x80030F78 */
132	uint32_t VCSR_CTL; /* 0x80030F80 */
133	uint32_t VCSR_TO; /* 0x80030F84 */
134	uint32_t V_AMERR; /* 0x80030F88 */
135	uint32_t VAERR; /* 0x80030F8C */
136	uint32_t Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */
137	uint32_t VCSR_CLR; /* 0x80030FF4 */
138	uint32_t VCSR_SET; /* 0x80030FF8 */
139	uint32_t VCSR_BS; /* 0x80030FFC */
140	} Universe_Memory;
141
142	volatile Universe_Memory *UNIVERSE =
143	(volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE;
144
145	/********************************************************************
146	********************************************************************
147	******* *******
148	******* *******
149	******* *******
150	********************************************************************
151	********************************************************************/
152
153	/*
154	* Initializes the UNIVERSE chip. This routine is called automatically
155	* by the boot code. This routine should be called by user code only if
156	* a complete SCORE603e VME initialization is required.
157	*/
158
159	void initialize_universe()
160	{
161	uint32_t jumper_selection;
162	uint32_t pci_id;
163
164	/*
165	* Read the VME jumper location to determine the VME base address
166	*/
167	jumper_selection = PCI_bus_read(
168	(volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR );
169	printk("initialize_universe: Read 0x%x = 0x%x\n",
170	SCORE603E_VME_JUMPER_ADDR, jumper_selection);
171	jumper_selection = (jumper_selection >> 3) & 0x1f;
172
173	/*
174	* Verify the UNIVERSE CHIP ID
175	*/
176	pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE );
177
178	/*
179	* compare to known ID
180	*/
181	if (pci_id != SCORE603E_UNIVERSE_CHIP_ID ){
182	printk ("Invalid SCORE603E_UNIVERSE_CHIP_ID: 0x08%" PRId32 "\n", pci_id);
183	rtems_fatal_error_occurred( 0x603e0bad );
184	} else {
185	printk("initialize_universe: Reg 0x%x read 0x%x\n",
186	SCORE603E_IO_VME_UNIVERSE_BASE, pci_id );
187	}
188
189	/*
190	* Do not modify the DINK setup of the universe chip.
191	*/
192	}
193
194	/*
195	* Set the slave VME base address to the specified base address.
196	* Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
197	* Slave Image 0 registers.
198	*/
199	void set_vme_base_address (
200	uint32_t base_address
201	)
202	{
203	volatile uint32_t temp;
204
205	/*
206	* Calculate the current size of the Slave VME image 0
207	*/
208	temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
209	( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
210
211	/*
212	* Set the VMEbus Slave Image 0 Base Address to be
213	* the specifed base address on VSI0_BS register.
214	*/
215	PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
216
217	/*
218	* Update the VMEbus Slave Image 0 Bound Address.
219	*/
220	PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
221
222	/*
223	* Update the VMEbus Slave Image 0 Translation Offset
224	*/
225	temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
226	PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
227	}
228
229	/*
230	* Gets the VME base address
231	*/
232	uint32_t get_vme_base_address ()
233	{
234	volatile uint32_t temp;
235
236	temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
237	temp &= 0xFFFFF000;
238	return (temp);
239	}
240
241	uint32_t get_vme_slave_size()
242	{
243	volatile uint32_t temp;
244	temp = PCI_bus_read( &UNIVERSE->VSI0_BD);
245	temp &= 0xFFFFF000;
246	temp = temp - get_vme_base_address ();
247	return temp;
248	}
249
250	/*
251	* Set the size of the VME slave image
252	* Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
253	*/
254	void set_vme_slave_size (uint32_t size)
255	{
256	volatile uint32_t temp;
257
258	if (size<0)
259	size = 0;
260
261	if (size > 0x17FFFFF)
262	size = 0x17FFFFF;
263
264	/*
265	* Read the VME slave image base address
266	*/
267	temp = get_vme_base_address ();
268
269	/*
270	* Update the VMEbus Slave Image 0 Bound Address.
271	*/
272	temp = temp + (size & 0xFFFFF000);
273	PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
274	}

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c @ 31a5ec8

Download in other formats: