source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c @ 42b6dd2a

4.104.115
Last change on this file since 42b6dd2a was 42b6dd2a, checked in by Jennifer Averett <Jennifer.Averett@…>, on 05/05/09 at 16:24:04

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, startup/linkcmds, timer/timer.c, tod/tod.c, vme/VMEConfig.h: Updated and tested with latest interrupt source. Modified with latest memory allocation, but this needs testing.
  • irq/no_pic.c: New file.
  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989-2009.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 * $Id$
11 */
12
13#include <rtems.h>
14#include <assert.h>
15#include <stdio.h>
16#include <inttypes.h>
17
18#include <bsp.h>
19#include <bsp/irq.h>
20#include "PCI.h"
21
22/*PAGE
23 *
24 *  SCORE603e_FLASH_Disable
25 */
26
27unsigned int SCORE603e_FLASH_Disable(
28  uint32_t                       area                           /* IN  */
29)
30{
31  uint8_t         value;
32
33  value = *SCORE603E_BOARD_CTRL_REG;
34  value = value | (~SCORE603E_BRD_FLASH_DISABLE_MASK);
35  *SCORE603E_BOARD_CTRL_REG = value;
36
37  return RTEMS_SUCCESSFUL;
38}
39
40unsigned int SCORE603e_FLASH_verify_enable( void )
41{
42  volatile uint8_t         *Ctrl_Status_Register =
43           (void *)SCORE603E_BOARD_CTRL_REG;
44  uint8_t          ctrl_value;
45  uint32_t         pci_value;
46
47  ctrl_value = *Ctrl_Status_Register;
48  if ( ctrl_value & SCORE603E_BRD_FLASH_DISABLE_MASK ) {
49    printf ("Flash Writes Disabled by board control register %x\n",
50            ctrl_value );
51    assert( 0x0 );
52  }
53
54  pci_value = Read_pci_device_register( 0x800000A8 );
55  if (( pci_value & 0x00001000 ) == 0) {
56    printf("Error PCI A8 \n");
57    assert( 0x0 );
58  }
59
60  pci_value = Read_pci_device_register( 0x800000AC );
61  if ( pci_value & 0x02000000) {
62    printf("Error PCI AC \n");
63    assert( 0x0 );
64  }
65  return RTEMS_SUCCESSFUL;
66}
67
68unsigned int SCORE603e_FLASH_pci_reset_reg(
69  uint8_t          reg,
70  uint32_t         cmask,
71  uint32_t         mask
72)
73{
74  uint32_t         pci_value;
75  uint32_t         value;
76
77  pci_value = Read_pci_device_register( reg );
78  pci_value &= cmask;
79  pci_value |= mask;
80  Write_pci_device_register( reg, pci_value );
81  value = Read_pci_device_register(  reg );
82  if (value != pci_value) {
83    printf("Error PCI 0x%2"PRIX8" wrote 0x%8"PRIX32" read %8"PRIX32"\n", reg, pci_value, value);
84  }
85  return RTEMS_SUCCESSFUL;
86}
87
88/*PAGE
89 *
90 *  SCORE603e_FLASH_Enable_writes
91 */
92unsigned int SCORE603e_FLASH_Enable_writes(
93  uint32_t                       area                           /* IN  */
94)
95{
96  uint8_t          ctrl_value;
97  uint32_t         pci_value;
98
99  ctrl_value = *SCORE603E_BOARD_CTRL_REG;
100  ctrl_value = ctrl_value & 0xbf;
101  *SCORE603E_BOARD_CTRL_REG = ctrl_value;
102
103  pci_value = Read_pci_device_register( 0x800000A8 );
104  pci_value |= 0x00001000;
105  Write_pci_device_register( 0x800000A8, pci_value );
106
107  pci_value = Read_pci_device_register( 0x800000AC );
108  pci_value &=  (~0x02000000);
109  Write_pci_device_register( 0x000000AC, pci_value );
110
111  return RTEMS_SUCCESSFUL;
112}
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