source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c @ 31a5ec8

4.9
Last change on this file since 31a5ec8 was 31a5ec8, checked in by Jennifer Averett <Jennifer.Averett@…>, on May 5, 2009 at 4:18:06 PM

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with the latest powerpc isr source
  • irq/no_pic.c: New file.
  • irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.
  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989-2009.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 * $Id$
11 */
12
13#include <rtems.h>
14#include <assert.h>
15#include <stdio.h>
16
17#include <bsp.h>
18#include <bsp/irq.h>
19#include "PCI.h"
20
21/*PAGE
22 *
23 *  SCORE603e_FLASH_Disable
24 */
25
26unsigned int SCORE603e_FLASH_Disable(
27  uint32_t                       area                           /* IN  */
28)
29{
30  uint8_t         value;
31
32  value = *SCORE603E_BOARD_CTRL_REG;
33  value = value | (~SCORE603E_BRD_FLASH_DISABLE_MASK);
34  *SCORE603E_BOARD_CTRL_REG = value;
35
36  return RTEMS_SUCCESSFUL;
37}
38
39unsigned int SCORE603e_FLASH_verify_enable()
40{
41  volatile uint8_t         *Ctrl_Status_Register =
42           (void *)SCORE603E_BOARD_CTRL_REG;
43  uint8_t          ctrl_value;
44  uint32_t         pci_value;
45
46  ctrl_value = *Ctrl_Status_Register;
47  if ( ctrl_value & SCORE603E_BRD_FLASH_DISABLE_MASK ) {
48    printf ("Flash Writes Disabled by board control register %x\n",
49            ctrl_value );
50    assert( 0x0 );
51  }
52
53  pci_value = Read_pci_device_register( 0x800000A8 );
54  if (( pci_value & 0x00001000 ) == 0) {
55    printf("Error PCI A8 \n");
56    assert( 0x0 );
57  }
58
59  pci_value = Read_pci_device_register( 0x800000AC );
60  if ( pci_value & 0x02000000) {
61    printf("Error PCI AC \n");
62    assert( 0x0 );
63  }
64  return RTEMS_SUCCESSFUL;
65}
66
67unsigned int SCORE603e_FLASH_pci_reset_reg(
68  uint8_t          reg,
69  uint32_t         cmask,
70  uint32_t         mask
71)
72{
73  uint32_t         pci_value;
74  uint32_t         value;
75
76  pci_value = Read_pci_device_register( reg );
77  pci_value &= cmask;
78  pci_value |= mask;
79  Write_pci_device_register( reg, pci_value );
80  value = Read_pci_device_register(  reg );
81  if (value != pci_value) {
82    printf("Error PCI %x wrote %x read %x\n", reg, pci_value, value);
83  }
84  return RTEMS_SUCCESSFUL;
85}
86
87/*PAGE
88 *
89 *  SCORE603e_FLASH_Enable_writes
90 */
91unsigned int SCORE603e_FLASH_Enable_writes(
92  uint32_t                       area                           /* IN  */
93)
94{
95  uint8_t          ctrl_value;
96  uint32_t         pci_value;
97
98  ctrl_value = *SCORE603E_BOARD_CTRL_REG;
99  ctrl_value = ctrl_value & 0xbf;
100  *SCORE603E_BOARD_CTRL_REG = ctrl_value;
101
102  pci_value = Read_pci_device_register( 0x800000A8 );
103  pci_value |= 0x00001000;
104  Write_pci_device_register( 0x800000A8, pci_value );
105
106  pci_value = Read_pci_device_register( 0x800000AC );
107  pci_value &=  (~0x02000000);
108  Write_pci_device_register( 0x000000AC, pci_value );
109
110  return RTEMS_SUCCESSFUL;
111}
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