1 | /* |
---|
2 | * COPYRIGHT (c) 1989-2014. |
---|
3 | * On-Line Applications Research Corporation (OAR). |
---|
4 | * |
---|
5 | * The license and distribution terms for this file may be |
---|
6 | * found in the file LICENSE in this distribution or at |
---|
7 | * http://www.rtems.org/license/LICENSE. |
---|
8 | */ |
---|
9 | |
---|
10 | #include <rtems.h> |
---|
11 | #include <assert.h> |
---|
12 | #include <stdio.h> |
---|
13 | |
---|
14 | #include <bsp.h> |
---|
15 | |
---|
16 | /* |
---|
17 | * Forced delay to get around timing problems with the UNIVERSE chip. The |
---|
18 | * two nops are used so that the delay works for varying clock frequencies, |
---|
19 | * up to 66 Mhz, with margin. Each nop averages about 1 1/2 clock ticks, |
---|
20 | * and since there are 2 nops, this routine takes about 3 clock ticks, |
---|
21 | * which on a worst case 66 Mhz board, is 45 nanosecond. This time period |
---|
22 | * is sufficient to guarantee a work-around to the UNIVERSE chip timing |
---|
23 | * problem. The problem is that when there are two successive accesses to |
---|
24 | * an UNIVERSE register, without sufficient delay, the second access will |
---|
25 | * not work correctly. |
---|
26 | */ |
---|
27 | static void PCI_bus_delay (void) |
---|
28 | { |
---|
29 | __asm__ volatile ("nop"); |
---|
30 | __asm__ volatile ("nop"); |
---|
31 | } |
---|
32 | |
---|
33 | /* |
---|
34 | * PCI_bus_write |
---|
35 | */ |
---|
36 | void PCI_bus_write( |
---|
37 | volatile uint32_t * _addr, /* IN */ |
---|
38 | uint32_t _data /* IN */ |
---|
39 | ) |
---|
40 | { |
---|
41 | _data = Convert_Endian_32( _data ); |
---|
42 | *_addr = _data; |
---|
43 | } |
---|
44 | |
---|
45 | uint32_t PCI_bus_read( |
---|
46 | volatile uint32_t * _addr /* IN */ |
---|
47 | ) |
---|
48 | { |
---|
49 | uint32_t data; |
---|
50 | |
---|
51 | data = *_addr; |
---|
52 | data = Convert_Endian_32( data ); |
---|
53 | return data; |
---|
54 | } |
---|
55 | /* |
---|
56 | * PCI Configuration Cycle Read/Write Access which is used to access all of |
---|
57 | * devices registers on the PCI bus. i.e.: Universe, Ethernet & PMC. |
---|
58 | */ |
---|
59 | uint32_t Read_pci_device_register( |
---|
60 | uint32_t address |
---|
61 | ) |
---|
62 | { |
---|
63 | uint32_t data; |
---|
64 | |
---|
65 | /* |
---|
66 | * Write the PCI configuration address |
---|
67 | */ |
---|
68 | PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address ); |
---|
69 | |
---|
70 | /* |
---|
71 | * Delay needed when running out of DRAM |
---|
72 | */ |
---|
73 | PCI_bus_delay (); |
---|
74 | |
---|
75 | /* |
---|
76 | * read data |
---|
77 | */ |
---|
78 | data = PCI_bus_read( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA ); |
---|
79 | |
---|
80 | return data; |
---|
81 | } |
---|
82 | |
---|
83 | void Write_pci_device_register( |
---|
84 | uint32_t address, |
---|
85 | uint32_t data |
---|
86 | ) |
---|
87 | { |
---|
88 | /* |
---|
89 | * Write the PCI configuration address |
---|
90 | */ |
---|
91 | PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address ); |
---|
92 | |
---|
93 | /* |
---|
94 | * Delay needed when running out of DRAM |
---|
95 | */ |
---|
96 | PCI_bus_delay (); |
---|
97 | |
---|
98 | /* |
---|
99 | * write data |
---|
100 | */ |
---|
101 | PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA, data ); |
---|
102 | } |
---|