source: rtems/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c @ 5ce16e9

4.104.11
Last change on this file since 5ce16e9 was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 21, 2004 at 4:01:48 PM

Remove duplicate white lines.

  • Property mode set to 100644
File size: 2.2 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 * $Id$
7 */
8
9#include <rtems.h>
10#include <assert.h>
11#include <stdio.h>
12
13#include <bsp.h>
14
15/*
16 * Forced delay to get around timing problems with the UNIVERSE chip.  The
17 * two nops are used so that the delay works for varying clock frequencies,
18 * up to 66 Mhz, with margin.  Each nop averages about 1 1/2 clock ticks,
19 * and since there are 2 nops, this routine takes about 3 clock ticks,
20 * which on a worst case 66 Mhz board, is 45 nanosecond. This time period
21 * is sufficient to guarantee a work-around to the UNIVERSE chip timing
22 * problem.  The problem is that when there are two successive accesses to
23 * an UNIVERSE register, without sufficient delay, the second access will
24 * not work correctly.
25 */
26void PCI_bus_delay ()
27{
28  asm(" nop");
29  asm(" nop");
30}
31
32/*
33 * PCI_bus_write
34 */
35void PCI_bus_write(
36  volatile uint32_t         * _addr,                  /* IN */
37  uint32_t         _data                              /* IN */
38)
39{
40  _data = Convert_Endian_32( _data );
41  *_addr = _data;
42}
43
44uint32_t         PCI_bus_read(
45  volatile uint32_t         *  _addr                  /* IN */
46)
47{
48  uint32_t         data;
49
50  data = *_addr;
51  data = Convert_Endian_32( data );
52  return data;
53}
54/*
55 * PCI Configuration Cycle Read/Write Access which is used to access all of
56 * devices registers on the PCI bus.  i.e.: Universe, Ethernet & PMC.
57 */
58
59uint32_t         Read_pci_device_register(
60  uint32_t         address
61)
62{
63  uint32_t         data;
64
65  /*
66   * Write the PCI configuration address
67   */
68   PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
69
70  /*
71   *  Delay needed when running out of DRAM
72   */
73   PCI_bus_delay ();
74
75  /*
76   * read data
77   */
78  data = PCI_bus_read( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA );
79
80  return data;
81}
82
83void  Write_pci_device_register(
84  uint32_t         address,
85  uint32_t         data
86)
87{
88  /*
89   * Write the PCI configuration address
90   */
91   PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
92
93  /*
94   *  Delay needed when running out of DRAM
95   */
96   PCI_bus_delay ();
97
98  /*
99   * write data
100   */
101  PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA, data );
102}
Note: See TracBrowser for help on using the repository browser.