1 | /* |
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2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Obere Lagerstr. 30 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <assert.h> |
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16 | |
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17 | #include <rtems/bspsmp.h> |
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18 | |
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19 | #include <libcpu/powerpc-utility.h> |
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20 | |
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21 | #include <bsp.h> |
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22 | #include <bsp/mmu.h> |
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23 | #include <bsp/qoriq.h> |
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24 | #include <bsp/vectors.h> |
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25 | #include <bsp/irq-generic.h> |
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26 | #include <bsp/linker-symbols.h> |
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27 | |
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28 | LINKER_SYMBOL(bsp_exc_vector_base); |
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29 | |
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30 | void _start_core_1(void); |
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31 | |
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32 | #define CORE_COUNT 2 |
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33 | |
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34 | #define ONE_CORE(core) (1 << (core)) |
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35 | |
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36 | #define ALL_CORES ((1 << CORE_COUNT) - 1) |
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37 | |
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38 | #define IPI_INDEX 0 |
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39 | |
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40 | #define TLB_BEGIN 8 |
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41 | |
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42 | #define TLB_END 16 |
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43 | |
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44 | #define TLB_COUNT (TLB_END - TLB_BEGIN) |
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45 | |
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46 | /* |
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47 | * These values can be obtained with the debugger or a look into the |
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48 | * U-Boot sources (arch/powerpc/cpu/mpc85xx/release.S). |
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49 | */ |
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50 | #if 1 |
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51 | #define BOOT_BEGIN 0x1fff0000 |
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52 | #define BOOT_LAST 0x1fffffff |
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53 | #define SPIN_TABLE (BOOT_BEGIN + 0xf2a0) |
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54 | #else |
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55 | #define BOOT_BEGIN 0x3fff0000 |
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56 | #define BOOT_LAST 0x3fffffff |
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57 | #define SPIN_TABLE (BOOT_BEGIN + 0xf240) |
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58 | #endif |
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59 | |
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60 | #define TLB_BEGIN 8 |
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61 | |
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62 | #define TLB_END 16 |
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63 | |
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64 | #define TLB_COUNT (TLB_END - TLB_BEGIN) |
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65 | |
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66 | typedef struct { |
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67 | uint32_t addr_upper; |
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68 | uint32_t addr_lower; |
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69 | uint32_t r3_upper; |
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70 | uint32_t r3_lower; |
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71 | uint32_t reserved; |
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72 | uint32_t pir; |
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73 | uint32_t r6_upper; |
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74 | uint32_t r6_lower; |
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75 | } uboot_spin_table; |
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76 | |
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77 | static uint32_t initial_core_1_stack[4096 / sizeof(uint32_t)]; |
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78 | |
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79 | static void mmu_config_undo(void) |
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80 | { |
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81 | int i = 0; |
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82 | |
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83 | for (i = TLB_BEGIN; i < TLB_END; ++i) { |
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84 | qoriq_tlb1_invalidate(i); |
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85 | } |
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86 | } |
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87 | |
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88 | static void release_core_1(void) |
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89 | { |
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90 | const Per_CPU_Control *second_cpu = _Per_CPU_Get_by_index(1); |
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91 | uboot_spin_table *spin_table = (uboot_spin_table *) SPIN_TABLE; |
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92 | qoriq_mmu_context mmu_context; |
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93 | |
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94 | qoriq_mmu_context_init(&mmu_context); |
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95 | qoriq_mmu_add(&mmu_context, BOOT_BEGIN, BOOT_LAST, 0, 0, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW); |
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96 | qoriq_mmu_partition(&mmu_context, TLB_COUNT); |
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97 | qoriq_mmu_write_to_tlb1(&mmu_context, TLB_BEGIN); |
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98 | |
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99 | spin_table->pir = 1; |
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100 | spin_table->r3_lower = (uint32_t) second_cpu->interrupt_stack_high; |
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101 | spin_table->addr_upper = 0; |
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102 | rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table)); |
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103 | ppc_synchronize_data(); |
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104 | spin_table->addr_lower = (uint32_t) _start_core_1; |
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105 | rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table)); |
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106 | |
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107 | mmu_config_undo(); |
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108 | } |
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109 | |
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110 | void qoriq_secondary_cpu_initialize(void) |
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111 | { |
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112 | const Per_CPU_Control *second_cpu = _Per_CPU_Get_by_index(1); |
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113 | |
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114 | /* Disable decrementer */ |
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115 | PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE); |
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116 | |
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117 | /* Initialize exception handler */ |
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118 | ppc_exc_initialize_with_vector_base( |
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119 | (uintptr_t) second_cpu->interrupt_stack_low, |
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120 | rtems_configuration_get_interrupt_stack_size(), |
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121 | bsp_exc_vector_base |
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122 | ); |
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123 | |
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124 | /* Now it is possible to make the code execute only */ |
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125 | qoriq_mmu_change_perm( |
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126 | FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, |
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127 | FSL_EIS_MAS3_SX, |
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128 | FSL_EIS_MAS3_SR |
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129 | ); |
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130 | |
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131 | /* Initialize interrupt support */ |
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132 | bsp_interrupt_facility_initialize(); |
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133 | |
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134 | bsp_interrupt_vector_enable(QORIQ_IRQ_IPI_0); |
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135 | |
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136 | rtems_smp_secondary_cpu_initialize(); |
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137 | } |
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138 | |
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139 | static void ipi_handler(void *arg) |
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140 | { |
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141 | rtems_smp_process_interrupt(); |
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142 | } |
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143 | |
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144 | uint32_t _CPU_SMP_Initialize(uint32_t configured_cpu_count) |
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145 | { |
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146 | rtems_status_code sc; |
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147 | uint32_t cores = configured_cpu_count < CORE_COUNT ? |
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148 | configured_cpu_count : CORE_COUNT; |
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149 | |
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150 | sc = rtems_interrupt_handler_install( |
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151 | QORIQ_IRQ_IPI_0, |
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152 | "IPI", |
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153 | RTEMS_INTERRUPT_UNIQUE, |
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154 | ipi_handler, |
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155 | NULL |
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156 | ); |
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157 | assert(sc == RTEMS_SUCCESSFUL); |
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158 | |
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159 | if (cores > 1) { |
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160 | release_core_1(); |
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161 | } |
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162 | |
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163 | return cores; |
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164 | } |
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165 | |
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166 | void bsp_smp_broadcast_interrupt(void) |
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167 | { |
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168 | uint32_t self = ppc_processor_id(); |
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169 | qoriq.pic.per_cpu [self].ipidr [IPI_INDEX].reg = ALL_CORES; |
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170 | } |
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171 | |
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172 | void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) |
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173 | { |
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174 | uint32_t self = ppc_processor_id(); |
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175 | qoriq.pic.per_cpu [self].ipidr [IPI_INDEX].reg = |
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176 | ONE_CORE(target_processor_index); |
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177 | } |
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