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start.S @ f2e6c3e

4.115

Last change on this file since f2e6c3e was f2e6c3e, checked in by Sebastian Huber <sebastian.huber@…>, on 01/13/15 at 10:38:18
bsp/qoriq: Add T2080RDB and T4240RDB variants
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File size: 6.8 KB

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1	/**
2	* @file
3	*
4	* @ingroup qoriq
5	*
6	* @brief BSP start.
7	*/
8
9	/*
10	* Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Dornierstr. 4
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.org/license/LICENSE.
21	*/
22
23	#include <rtems/score/percpu.h>
24
25	#include <bspopts.h>
26
27	#include <libcpu/powerpc-utility.h>
28
29	#include <bsp/vectors.h>
30
31	#define FIRST_TLB 0
32	#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
33	#define INITIAL_MSR r14
34
35	.globl _start
36	#ifdef RTEMS_SMP
37	#if QORIQ_THREAD_COUNT > 1
38	.globl _start_thread
39	#endif
40	.globl _start_secondary_processor
41	#endif
42	.globl bsp_exc_vector_base
43
44	.section ".bsp_start_text", "ax"
45
46	_start:
47	bl .Linit
48
49	#ifdef HAS_UBOOT
50	bl bsp_uboot_copy_board_info
51	#endif /* HAS_UBOOT */
52
53	/* Initial MMU setup */
54	bl qoriq_tlb1_ts_0_only
55	li r3, SCRATCH_TLB
56	li r4, FSL_EIS_MAS1_TS
57	li r5, FSL_EIS_MAS2_I
58	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
59	li r7, 0
60	li r8, 0
61	li r9, 11
62	bl qoriq_tlb1_write
63
64	/* MSR initialization */
65	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
66	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
67	mtmsr r0
68
69	/* Initialize start stack */
70	LWI r1, start_stack_end - PPC_MINIMUM_STACK_FRAME_SIZE
71	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
72	li r0, 0
73	stw r0, 0(r1)
74
75	/* Copy fast text */
76	LWI r3, bsp_section_fast_text_begin
77	LWI r4, bsp_section_fast_text_load_begin
78	LWI r5, bsp_section_fast_text_size
79	bl .Lcopy
80
81	/* Copy read-only data */
82	LWI r3, bsp_section_rodata_begin
83	LWI r4, bsp_section_rodata_load_begin
84	LWI r5, bsp_section_rodata_size
85	bl .Lcopy
86
87	/* Copy fast data */
88	LWI r3, bsp_section_fast_data_begin
89	LWI r4, bsp_section_fast_data_load_begin
90	LWI r5, bsp_section_fast_data_size
91	bl .Lcopy
92
93	/* Copy data */
94	LWI r3, bsp_section_data_begin
95	LWI r4, bsp_section_data_load_begin
96	LWI r5, bsp_section_data_size
97	bl .Lcopy
98
99	/* NULL pointer access protection (only core 0 has to do this) */
100	mfspr r3, BOOKE_PIR
101	cmpwi r3, 0
102	bne .Lnull_area_setup_done
103	LWI r3, bsp_section_start_begin
104	srawi r3, r3, 2
105	mtctr r3
106	li r3, -4
107	LWI r4, 0x44000002
108	.Lnull_area_setup_loop:
109	stwu r4, 4(r3)
110	bdnz .Lnull_area_setup_loop
111	.Lnull_area_setup_done:
112
113	/* Configure MMU */
114	li r3, FIRST_TLB
115	li r4, SCRATCH_TLB
116	bl qoriq_mmu_config
117	mtmsr INITIAL_MSR
118	li r3, SCRATCH_TLB
119	bl qoriq_tlb1_invalidate
120
121	/* Clear SBSS */
122	LWI r3, bsp_section_sbss_begin
123	LWI r4, bsp_section_sbss_size
124	bl bsp_start_zero
125
126	/* Clear BSS */
127	LWI r3, bsp_section_bss_begin
128	LWI r4, bsp_section_bss_size
129	bl bsp_start_zero
130
131	/* Set up EABI and SYSV environment */
132	bl __eabi
133
134	/* Clear command line */
135	li r3, 0
136
137	bl boot_card
138
139	.Lcopy:
140	cmpw r3, r4
141	beqlr
142	b memcpy
143
144	/* Do not use r3 here, since this could be the U-Boot board info */
145	.Linit:
146	/* Reset time base */
147	li r0, 0
148	mtspr TBWU, r0
149	mtspr TBWL, r0
150
151	/* Disable decrementer */
152	mfspr r0, BOOKE_TCR
153	LWI r4, BOOKE_TCR_DIE
154	andc r0, r0, r4
155	mtspr BOOKE_TCR, r0
156
157	#ifdef QORIQ_INITIAL_SPEFSCR
158	/* SPEFSCR initialization */
159	LWI r0, QORIQ_INITIAL_SPEFSCR
160	mtspr FSL_EIS_SPEFSCR, r0
161	#endif
162
163	/* Set small-data anchors */
164	LA r2, _SDA2_BASE_
165	LA r13, _SDA_BASE_
166
167	blr
168
169	#ifdef RTEMS_SMP
170	#if QORIQ_THREAD_COUNT > 1
171	_start_thread:
172	/* Adjust PIR */
173	mfspr r0, BOOKE_PIR
174	srawi r0, r0, 2
175	ori r0, r0, 1
176	mtspr BOOKE_PIR, r0
177
178	bl .Linit
179
180	/* Initialize start stack */
181	GET_SELF_CPU_CONTROL r3
182	lwz r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
183	subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
184	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
185	li r0, 0
186	stw r0, 0(r1)
187
188	b qoriq_start_thread
189	#endif
190	_start_secondary_processor:
191
192	bl .Linit
193
194	/* Get start stack */
195	mr r1, r3
196
197	/* Initial MMU setup */
198	bl qoriq_tlb1_ts_0_only
199	li r3, SCRATCH_TLB
200	li r4, FSL_EIS_MAS1_TS
201	li r5, FSL_EIS_MAS2_I
202	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
203	li r7, 0
204	li r8, 0
205	li r9, 11
206	bl qoriq_tlb1_write
207
208	/* MSR initialization */
209	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
210	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
211	mtmsr r0
212
213	/* Initialize start stack */
214	subi r1, r1, PPC_MINIMUM_STACK_FRAME_SIZE
215	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
216	li r0, 0
217	stw r0, 0(r1)
218
219	/* Configure MMU */
220	li r3, FIRST_TLB
221	li r4, SCRATCH_TLB
222	bl qoriq_mmu_config
223	mtmsr INITIAL_MSR
224	li r3, SCRATCH_TLB
225	bl qoriq_tlb1_invalidate
226
227	b bsp_start_on_secondary_processor
228	#endif /* RTEMS_SMP */
229
230	/* Exception vector prologues area */
231	.section ".bsp_start_text", "ax"
232	.align 4
233	bsp_exc_vector_base:
234	stw r1, ppc_exc_lock_crit@sdarel(r13)
235	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
236	li r4, -32767
237	b ppc_exc_wrap_bookE_crit
238	stwu r1, -EXC_GENERIC_SIZE(r1)
239	stw r4, GPR4_OFFSET(r1)
240	li r4, 2
241	b ppc_exc_wrap_nopush_e500_mchk
242	stwu r1, -EXC_GENERIC_SIZE(r1)
243	stw r4, GPR4_OFFSET(r1)
244	li r4, 3
245	b ppc_exc_wrap_nopush_std
246	stwu r1, -EXC_GENERIC_SIZE(r1)
247	stw r4, GPR4_OFFSET(r1)
248	li r4, 4
249	b ppc_exc_wrap_nopush_std
250	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
251	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
252	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
253	li r4, -32763
254	#endif
255	b ppc_exc_wrap_async_normal
256	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
257	nop
258	nop
259	#endif
260	stwu r1, -EXC_GENERIC_SIZE(r1)
261	stw r4, GPR4_OFFSET(r1)
262	li r4, 6
263	b ppc_exc_wrap_nopush_std
264	stwu r1, -EXC_GENERIC_SIZE(r1)
265	stw r4, GPR4_OFFSET(r1)
266	li r4, 7
267	b ppc_exc_wrap_nopush_std
268	stwu r1, -EXC_GENERIC_SIZE(r1)
269	stw r4, GPR4_OFFSET(r1)
270	li r4, 8
271	b ppc_exc_wrap_nopush_std
272	system_call:
273	stwu r1, -EXC_GENERIC_SIZE(r1)
274	stw r4, GPR4_OFFSET(r1)
275	li r4, 12
276	b ppc_exc_wrap_nopush_std
277	stwu r1, -EXC_GENERIC_SIZE(r1)
278	stw r4, GPR4_OFFSET(r1)
279	li r4, 24
280	b ppc_exc_wrap_nopush_std
281	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
282	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
283	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
284	li r4, -32752
285	#endif
286	b ppc_exc_wrap_async_normal
287	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
288	nop
289	nop
290	#endif
291	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
292	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
293	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
294	li r4, -32749
295	#endif
296	b ppc_exc_wrap_async_normal
297	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
298	nop
299	nop
300	#endif
301	stw r1, ppc_exc_lock_crit@sdarel(r13)
302	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
303	li r4, -32748
304	b ppc_exc_wrap_bookE_crit
305	stwu r1, -EXC_GENERIC_SIZE(r1)
306	stw r4, GPR4_OFFSET(r1)
307	li r4, 18
308	b ppc_exc_wrap_nopush_std
309	stwu r1, -EXC_GENERIC_SIZE(r1)
310	stw r4, GPR4_OFFSET(r1)
311	li r4, 17
312	b ppc_exc_wrap_nopush_std
313	stwu r1, -EXC_GENERIC_SIZE(r1)
314	stw r4, GPR4_OFFSET(r1)
315	li r4, 13
316	b ppc_exc_wrap_nopush_bookE_crit
317	stwu r1, -EXC_GENERIC_SIZE(r1)
318	stw r4, GPR4_OFFSET(r1)
319	li r4, 10
320	b ppc_exc_wrap_nopush_std
321	stwu r1, -EXC_GENERIC_SIZE(r1)
322	stw r4, GPR4_OFFSET(r1)
323	li r4, 25
324	b ppc_exc_wrap_nopush_std
325	stwu r1, -EXC_GENERIC_SIZE(r1)
326	stw r4, GPR4_OFFSET(r1)
327	li r4, 26
328	b ppc_exc_wrap_nopush_std
329	stwu r1, -EXC_GENERIC_SIZE(r1)
330	stw r4, GPR4_OFFSET(r1)
331	li r4, 15
332	b ppc_exc_wrap_nopush_std
333
334	/* Start stack area */
335	.section ".bsp_rwextra", "aw", @nobits
336	.align 4
337	.space 4096
338	start_stack_end:

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