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start.S @ bd39add

4.115

Last change on this file since bd39add was bd39add, checked in by Sebastian Huber <sebastian.huber@…>, on 05/31/13 at 08:08:43
bsp/qoriq: Add SMP support
Property mode set to `100644`
File size: 6.6 KB

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1	/**
2	* @file
3	*
4	* @ingroup qoriq
5	*
6	* @brief BSP start.
7	*/
8
9	/*
10	* Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Dornierstr. 4
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.com/license/LICENSE.
21	*/
22
23	#include <bspopts.h>
24
25	#include <libcpu/powerpc-utility.h>
26
27	#include <bsp/vectors.h>
28
29	#define FIRST_TLB 0
30	#define SCRATCH_TLB 15
31	#define INITIAL_MSR r14
32	#define UBOOT_BOARD_INFO r15
33
34	.globl _start
35	.globl _start_core_1
36	.globl bsp_exc_vector_base
37
38	.section ".bsp_start_text", "ax"
39
40	_start:
41	/* Reset time base */
42	li r0, 0
43	mtspr TBWU, r0
44	mtspr TBWL, r0
45
46	#ifdef HAS_UBOOT
47	mr UBOOT_BOARD_INFO, r3
48	#endif /* HAS_UBOOT */
49
50	/* Initial MMU setup */
51	bl qoriq_tlb1_ts_0_only
52	li r3, SCRATCH_TLB
53	li r4, FSL_EIS_MAS1_TS
54	li r5, FSL_EIS_MAS2_I
55	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
56	li r7, 0
57	li r8, 11
58	bl qoriq_tlb1_write
59
60	/* MSR initialization */
61	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
62	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
63	mtmsr r0
64
65	/* SPEFSCR initialization */
66	LWI r0, QORIQ_INITIAL_SPEFSCR
67	mtspr FSL_EIS_SPEFSCR, r0
68
69	/* Initialize start stack */
70	LWI r1, start_stack_end
71	subi r1, r1, 16
72	li r0, 0
73	stw r0, 0(r1)
74
75	/* Copy fast text */
76	LWI r3, bsp_section_fast_text_begin
77	LWI r4, bsp_section_fast_text_load_begin
78	LWI r5, bsp_section_fast_text_size
79	bl copy
80
81	/* Copy read-only data */
82	LWI r3, bsp_section_rodata_begin
83	LWI r4, bsp_section_rodata_load_begin
84	LWI r5, bsp_section_rodata_size
85	bl copy
86
87	/* Copy small read-only data */
88	LWI r3, bsp_section_sdata2_begin
89	LWI r4, bsp_section_sdata2_load_begin
90	LWI r5, bsp_section_sdata2_size
91	bl copy
92
93	/* Copy fast data */
94	LWI r3, bsp_section_fast_data_begin
95	LWI r4, bsp_section_fast_data_load_begin
96	LWI r5, bsp_section_fast_data_size
97	bl copy
98
99	/* Copy data */
100	LWI r3, bsp_section_data_begin
101	LWI r4, bsp_section_data_load_begin
102	LWI r5, bsp_section_data_size
103	bl copy
104
105	/* Copy small data */
106	LWI r3, bsp_section_sdata_begin
107	LWI r4, bsp_section_sdata_load_begin
108	LWI r5, bsp_section_sdata_size
109	bl copy
110
111	/* NULL pointer access protection (only core 0 has to do this) */
112	mfspr r3, BOOKE_PIR
113	cmpwi r3, 0
114	bne null_area_setup_done
115	LWI r3, bsp_section_start_begin
116	srawi r3, r3, 2
117	mtctr r3
118	li r3, -4
119	LWI r4, 0x44000002
120	null_area_setup_loop:
121	stwu r4, 4(r3)
122	bdnz null_area_setup_loop
123	null_area_setup_done:
124
125	/* Configure MMU */
126	li r3, FIRST_TLB
127	li r4, SCRATCH_TLB
128	bl qoriq_mmu_config
129	mtmsr INITIAL_MSR
130	li r3, SCRATCH_TLB
131	bl qoriq_tlb1_invalidate
132
133	/* Clear SBSS */
134	LWI r3, bsp_section_sbss_begin
135	LWI r4, bsp_section_sbss_size
136	bl bsp_start_zero
137
138	/* Clear BSS */
139	LWI r3, bsp_section_bss_begin
140	LWI r4, bsp_section_bss_size
141	bl bsp_start_zero
142
143	#ifdef HAS_UBOOT
144	li r3, SCRATCH_TLB
145	li r4, 0
146	li r5, 0
147	li r6, FSL_EIS_MAS3_SR
148	mr r7, UBOOT_BOARD_INFO
149	li r8, 1
150	bl qoriq_tlb1_write
151	mr r3, UBOOT_BOARD_INFO
152	bl bsp_uboot_copy_board_info
153	li r3, SCRATCH_TLB
154	bl qoriq_tlb1_invalidate
155	#endif /* HAS_UBOOT */
156
157	/* Set up EABI and SYSV environment */
158	bl __eabi
159
160	/* Clear command line */
161	li r3, 0
162
163	bl boot_card
164
165	twiddle:
166	b twiddle
167
168	copy:
169	cmpw r3, r4
170	beqlr
171	b memcpy
172
173	_start_core_1:
174
175	/* Reset time base */
176	li r0, 0
177	mtspr TBWU, r0
178	mtspr TBWL, r0
179
180	/* Get start stack */
181	subi r1, r3, 16
182
183	/* Initial MMU setup */
184	bl qoriq_tlb1_ts_0_only
185	li r3, SCRATCH_TLB
186	li r4, FSL_EIS_MAS1_TS
187	li r5, FSL_EIS_MAS2_I
188	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
189	li r7, 0
190	li r8, 11
191	bl qoriq_tlb1_write
192
193	/* MSR initialization */
194	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
195	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
196	mtmsr r0
197
198	/* SPEFSCR initialization */
199	LWI r0, QORIQ_INITIAL_SPEFSCR
200	mtspr FSL_EIS_SPEFSCR, r0
201
202	/* Initialize start stack */
203	li r0, 0
204	stw r0, 0(r1)
205
206	/* Configure MMU */
207	li r3, FIRST_TLB
208	li r4, SCRATCH_TLB
209	bl qoriq_mmu_config
210	mtmsr INITIAL_MSR
211	li r3, SCRATCH_TLB
212	bl qoriq_tlb1_invalidate
213
214	/* Set small-data anchors */
215	LA r2, _SDA2_BASE_
216	LA r13, _SDA_BASE_
217
218	b qoriq_secondary_cpu_initialize
219
220	b twiddle
221
222	/* Exception vector prologues area */
223	.section ".bsp_start_text", "ax"
224	.align 4
225	bsp_exc_vector_base:
226	stw r1, ppc_exc_lock_crit@sdarel(r13)
227	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
228	li r4, -32767
229	b ppc_exc_wrap_bookE_crit
230	stwu r1, -EXC_GENERIC_SIZE(r1)
231	stw r4, GPR4_OFFSET(r1)
232	li r4, 2
233	b ppc_exc_wrap_nopush_e500_mchk
234	stwu r1, -EXC_GENERIC_SIZE(r1)
235	stw r4, GPR4_OFFSET(r1)
236	li r4, 3
237	b ppc_exc_wrap_nopush_std
238	stwu r1, -EXC_GENERIC_SIZE(r1)
239	stw r4, GPR4_OFFSET(r1)
240	li r4, 4
241	b ppc_exc_wrap_nopush_std
242	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
243	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
244	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
245	li r4, -32763
246	#endif
247	b ppc_exc_wrap_async_normal
248	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
249	nop
250	nop
251	#endif
252	stwu r1, -EXC_GENERIC_SIZE(r1)
253	stw r4, GPR4_OFFSET(r1)
254	li r4, 6
255	b ppc_exc_wrap_nopush_std
256	stwu r1, -EXC_GENERIC_SIZE(r1)
257	stw r4, GPR4_OFFSET(r1)
258	li r4, 7
259	b ppc_exc_wrap_nopush_std
260	stwu r1, -EXC_GENERIC_SIZE(r1)
261	stw r4, GPR4_OFFSET(r1)
262	li r4, 8
263	b ppc_exc_wrap_nopush_std
264	system_call:
265	stwu r1, -EXC_GENERIC_SIZE(r1)
266	stw r4, GPR4_OFFSET(r1)
267	li r4, 12
268	b ppc_exc_wrap_nopush_std
269	stwu r1, -EXC_GENERIC_SIZE(r1)
270	stw r4, GPR4_OFFSET(r1)
271	li r4, 24
272	b ppc_exc_wrap_nopush_std
273	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
274	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
275	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
276	li r4, -32752
277	#endif
278	b ppc_exc_wrap_async_normal
279	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
280	nop
281	nop
282	#endif
283	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
284	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
285	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
286	li r4, -32749
287	#endif
288	b ppc_exc_wrap_async_normal
289	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
290	nop
291	nop
292	#endif
293	stw r1, ppc_exc_lock_crit@sdarel(r13)
294	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
295	li r4, -32748
296	b ppc_exc_wrap_bookE_crit
297	stwu r1, -EXC_GENERIC_SIZE(r1)
298	stw r4, GPR4_OFFSET(r1)
299	li r4, 18
300	b ppc_exc_wrap_nopush_std
301	stwu r1, -EXC_GENERIC_SIZE(r1)
302	stw r4, GPR4_OFFSET(r1)
303	li r4, 17
304	b ppc_exc_wrap_nopush_std
305	stwu r1, -EXC_GENERIC_SIZE(r1)
306	stw r4, GPR4_OFFSET(r1)
307	li r4, 13
308	b ppc_exc_wrap_nopush_bookE_crit
309	stwu r1, -EXC_GENERIC_SIZE(r1)
310	stw r4, GPR4_OFFSET(r1)
311	li r4, 10
312	b ppc_exc_wrap_nopush_std
313	stwu r1, -EXC_GENERIC_SIZE(r1)
314	stw r4, GPR4_OFFSET(r1)
315	li r4, 25
316	b ppc_exc_wrap_nopush_std
317	stwu r1, -EXC_GENERIC_SIZE(r1)
318	stw r4, GPR4_OFFSET(r1)
319	li r4, 26
320	b ppc_exc_wrap_nopush_std
321	stwu r1, -EXC_GENERIC_SIZE(r1)
322	stw r4, GPR4_OFFSET(r1)
323	li r4, 15
324	b ppc_exc_wrap_nopush_std
325
326	/* Start stack area */
327	.section ".bsp_rwextra", "aw", @nobits
328	.align 4
329	.space 4096
330	start_stack_end:

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