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start.S @ b615e9b

Last change on this file since b615e9b was b615e9b, checked in by Sebastian Huber <sebastian.huber@…>, on 07/27/17 at 13:16:36

bsp/qoriq: Simplify initialization

Do not flush/invalidate the caches. Instead enable the cache during the
low-level initialization and perform an explicit cache flush for the
read-only and fast-text sections.

Update #3082.
Update #3085.

Property mode set to 100644

File size: 8.2 KB

Line
1	/**
2	* @file
3	*
4	* @ingroup qoriq
5	*
6	* @brief BSP start.
7	*/
8
9	/*
10	* Copyright (c) 2010, 2016 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Dornierstr. 4
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.org/license/LICENSE.
21	*/
22
23	#include <rtems/score/percpu.h>
24
25	#include <bspopts.h>
26
27	#include <libcpu/powerpc-utility.h>
28
29	#include <bsp/vectors.h>
30
31	#if (QORIQ_INITIAL_MSR & MSR_FP) != 0
32	#define INITIALIZE_FPU
33	#endif
34
35	#define FIRST_TLB 0
36	#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
37	#define INITIAL_MSR r14
38	#define START_STACK r15
39	#define SAVED_LINK_REGISTER r16
40
41	.globl _start
42	#ifdef RTEMS_SMP
43	#if QORIQ_THREAD_COUNT > 1
44	.globl _start_thread
45	#endif
46	.globl _start_secondary_processor
47	#endif
48	.globl bsp_exc_vector_base
49
50	.section ".bsp_start_text", "ax"
51
52	_start:
53	bl .Linitearly
54	bl bsp_fdt_copy
55
56	/* Get start stack */
57	LWI START_STACK, start_stack_end
58
59	bl .Linitmore
60
61	/* Copy fast text */
62	LWI r3, bsp_section_fast_text_begin
63	LWI r4, bsp_section_fast_text_load_begin
64	LWI r5, bsp_section_fast_text_size
65	bl .Lcopy
66	LWI r3, bsp_section_fast_text_begin
67	LWI r4, bsp_section_fast_text_size
68	bl rtems_cache_flush_multiple_data_lines
69
70	/* Copy read-only data */
71	LWI r3, bsp_section_rodata_begin
72	LWI r4, bsp_section_rodata_load_begin
73	LWI r5, bsp_section_rodata_size
74	bl .Lcopy
75	LWI r3, bsp_section_rodata_begin
76	LWI r4, bsp_section_rodata_size
77	bl rtems_cache_flush_multiple_data_lines
78
79	/* Copy fast data */
80	LWI r3, bsp_section_fast_data_begin
81	LWI r4, bsp_section_fast_data_load_begin
82	LWI r5, bsp_section_fast_data_size
83	bl .Lcopy
84
85	/* Copy data */
86	LWI r3, bsp_section_data_begin
87	LWI r4, bsp_section_data_load_begin
88	LWI r5, bsp_section_data_size
89	bl .Lcopy
90
91	/* NULL pointer access protection (only core 0 has to do this) */
92	mfspr r3, BOOKE_PIR
93	cmpwi r3, 0
94	bne .Lnull_area_setup_done
95	LWI r3, bsp_section_start_begin
96	srawi r3, r3, 2
97	mtctr r3
98	li r3, -4
99	LWI r4, 0x44000002
100	.Lnull_area_setup_loop:
101	stwu r4, 4(r3)
102	bdnz .Lnull_area_setup_loop
103	.Lnull_area_setup_done:
104
105	li r3, 1
106	bl .Linitmmu
107
108	/* Clear SBSS */
109	LWI r3, bsp_section_sbss_begin
110	LWI r4, bsp_section_sbss_size
111	bl bsp_start_zero
112
113	/* Clear BSS */
114	LWI r3, bsp_section_bss_begin
115	LWI r4, bsp_section_bss_size
116	bl bsp_start_zero
117
118	/* Set up EABI and SYSV environment */
119	bl __eabi
120
121	/* Clear command line */
122	li r3, 0
123
124	bl boot_card
125
126	.Lcopy:
127	cmpw r3, r4
128	beqlr
129	b memcpy
130
131	.Linitearly:
132	/*
133	* Do not use r3 here, since it holds the FDT base pointer provided by
134	* the boot loader.
135	*/
136
137	/* Disable decrementer */
138	mfspr r0, BOOKE_TCR
139	LWI r4, BOOKE_TCR_DIE
140	andc r0, r0, r4
141	mtspr BOOKE_TCR, r0
142
143	#ifdef QORIQ_INITIAL_SPEFSCR
144	/* SPEFSCR initialization */
145	LWI r0, QORIQ_INITIAL_SPEFSCR
146	mtspr FSL_EIS_SPEFSCR, r0
147	#endif
148
149	#ifdef QORIQ_INITIAL_BUCSR
150	/* BUCSR initialization */
151	LWI r0, QORIQ_INITIAL_BUCSR
152	mtspr FSL_EIS_BUCSR, r0
153	isync
154	#endif
155
156	#ifdef QORIQ_INITIAL_HID0
157	/* HID0 initialization */
158	LWI r0, QORIQ_INITIAL_HID0
159	mtspr HID0, r0
160	#endif
161
162	/* Invalidate TLS anchor */
163	li r2, 0
164
165	/* Set small-data anchor */
166	LA r13, _SDA_BASE_
167
168	#ifdef RTEMS_SMP
169	SET_SELF_CPU_CONTROL r4
170	#endif
171
172	blr
173
174	.Linitmore:
175	mflr SAVED_LINK_REGISTER
176
177	/* Invalidate all TS1 MMU entries */
178	li r3, 1
179	bl qoriq_tlb1_invalidate_all_by_ts
180
181	/* Add TS1 entry for the first 4GiB of RAM */
182	li r3, SCRATCH_TLB
183	li r4, FSL_EIS_MAS1_TS
184	li r5, FSL_EIS_MAS2_M
185	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
186	li r7, 0
187	li r8, 0
188	li r9, 11
189	bl qoriq_tlb1_write
190
191	/* MSR initialization and use TS1 for address translation */
192	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
193	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
194	mtmsr r0
195	isync
196
197	/*
198	* Initialize start stack. Make sure that we do not share a cache line
199	* with the heap block management, since initial stacks for the
200	* secondary processors are allocated from the workspace.
201	*/
202	subi r1, START_STACK, 2 * PPC_DEFAULT_CACHE_LINE_SIZE
203	clrrwi r1, r1, PPC_DEFAULT_CACHE_LINE_POWER
204	li r0, 0
205	stw r0, 0(r1)
206
207	#ifdef INITIALIZE_FPU
208	bl .Linitfpu
209	#endif
210
211	mtlr SAVED_LINK_REGISTER
212	blr
213
214	.Linitmmu:
215	mflr SAVED_LINK_REGISTER
216
217	/* Configure MMU */
218	li r4, FIRST_TLB
219	li r5, SCRATCH_TLB
220	bl qoriq_mmu_config
221	mtmsr INITIAL_MSR
222	isync
223	li r3, SCRATCH_TLB
224	bl qoriq_tlb1_invalidate
225
226	mtlr SAVED_LINK_REGISTER
227	blr
228
229	#ifdef INITIALIZE_FPU
230	/*
231	* Write a value to the FPRs to initialize the hidden tag bits. See
232	* also "Core Software Initialization Requirements" of the e500mc
233	* reference manual for example.
234	*/
235	.Linitfpu:
236	li r0, 0
237	stw r0, 0(r1)
238	stw r0, 4(r1)
239	lfd f0, 0(r1)
240	fmr f1, f0
241	fmr f2, f0
242	fmr f3, f0
243	fmr f4, f0
244	fmr f5, f0
245	fmr f6, f0
246	fmr f7, f0
247	fmr f8, f0
248	fmr f9, f0
249	fmr f10, f0
250	fmr f11, f0
251	fmr f12, f0
252	fmr f13, f0
253	fmr f14, f0
254	fmr f15, f0
255	fmr f16, f0
256	fmr f17, f0
257	fmr f18, f0
258	fmr f19, f0
259	fmr f20, f0
260	fmr f21, f0
261	fmr f22, f0
262	fmr f23, f0
263	fmr f24, f0
264	fmr f25, f0
265	fmr f26, f0
266	fmr f27, f0
267	fmr f28, f0
268	fmr f29, f0
269	fmr f30, f0
270	fmr f31, f0
271	blr
272	#endif
273
274	#ifdef RTEMS_SMP
275	#if QORIQ_THREAD_COUNT > 1
276	_start_thread:
277	/* Adjust PIR */
278	mfspr r0, BOOKE_PIR
279	srawi r0, r0, 2
280	ori r0, r0, 1
281	mtspr BOOKE_PIR, r0
282
283	bl .Linitearly
284
285	/* Initialize start stack */
286	GET_SELF_CPU_CONTROL r3
287	lwz r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
288	subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
289	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
290	li r0, 0
291	stw r0, 0(r1)
292
293	#ifdef INITIALIZE_FPU
294	bl .Linitfpu
295	#endif
296
297	b qoriq_start_thread
298	#endif
299	_start_secondary_processor:
300	bl .Linitearly
301
302	/* Get start stack */
303	mr START_STACK, r3
304
305	bl .Linitmore
306	li r3, 0
307	bl .Linitmmu
308	b bsp_start_on_secondary_processor
309	#endif /* RTEMS_SMP */
310
311	/* Exception vector prologues area */
312	.section ".bsp_start_text", "ax"
313	.align 4
314	bsp_exc_vector_base:
315	stw r1, ppc_exc_lock_crit@sdarel(r13)
316	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
317	li r4, -32767
318	b ppc_exc_wrap_bookE_crit
319	stwu r1, -EXC_GENERIC_SIZE(r1)
320	stw r4, GPR4_OFFSET(r1)
321	li r4, 2
322	b ppc_exc_wrap_nopush_e500_mchk
323	stwu r1, -EXC_GENERIC_SIZE(r1)
324	stw r4, GPR4_OFFSET(r1)
325	li r4, 3
326	b ppc_exc_wrap_nopush_std
327	stwu r1, -EXC_GENERIC_SIZE(r1)
328	stw r4, GPR4_OFFSET(r1)
329	li r4, 4
330	b ppc_exc_wrap_nopush_std
331	stwu r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
332	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
333	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
334	li r4, -32763
335	#endif
336	b ppc_exc_wrap_async_normal
337	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
338	nop
339	nop
340	#endif
341	stwu r1, -EXC_GENERIC_SIZE(r1)
342	stw r4, GPR4_OFFSET(r1)
343	li r4, 6
344	b ppc_exc_wrap_nopush_std
345	stwu r1, -EXC_GENERIC_SIZE(r1)
346	stw r4, GPR4_OFFSET(r1)
347	li r4, 7
348	b ppc_exc_wrap_nopush_std
349	stwu r1, -EXC_GENERIC_SIZE(r1)
350	stw r4, GPR4_OFFSET(r1)
351	li r4, 8
352	b ppc_exc_wrap_nopush_std
353	system_call:
354	stwu r1, -EXC_GENERIC_SIZE(r1)
355	stw r4, GPR4_OFFSET(r1)
356	li r4, 12
357	b ppc_exc_wrap_nopush_std
358	stwu r1, -EXC_GENERIC_SIZE(r1)
359	stw r4, GPR4_OFFSET(r1)
360	li r4, 24
361	b ppc_exc_wrap_nopush_std
362	stwu r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
363	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
364	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
365	li r4, -32752
366	#endif
367	b ppc_exc_wrap_async_normal
368	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
369	nop
370	nop
371	#endif
372	stwu r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
373	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
374	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
375	li r4, -32749
376	#endif
377	b ppc_exc_wrap_async_normal
378	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
379	nop
380	nop
381	#endif
382	stw r1, ppc_exc_lock_crit@sdarel(r13)
383	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
384	li r4, -32748
385	b ppc_exc_wrap_bookE_crit
386	stwu r1, -EXC_GENERIC_SIZE(r1)
387	stw r4, GPR4_OFFSET(r1)
388	li r4, 18
389	b ppc_exc_wrap_nopush_std
390	stwu r1, -EXC_GENERIC_SIZE(r1)
391	stw r4, GPR4_OFFSET(r1)
392	li r4, 17
393	b ppc_exc_wrap_nopush_std
394	stwu r1, -EXC_GENERIC_SIZE(r1)
395	stw r4, GPR4_OFFSET(r1)
396	li r4, 13
397	b ppc_exc_wrap_nopush_bookE_crit
398	stwu r1, -EXC_GENERIC_SIZE(r1)
399	stw r4, GPR4_OFFSET(r1)
400	li r4, 10
401	b ppc_exc_wrap_nopush_std
402	stwu r1, -EXC_GENERIC_SIZE(r1)
403	stw r4, GPR4_OFFSET(r1)
404	li r4, 25
405	b ppc_exc_wrap_nopush_std
406	stwu r1, -EXC_GENERIC_SIZE(r1)
407	stw r4, GPR4_OFFSET(r1)
408	li r4, 26
409	b ppc_exc_wrap_nopush_std
410	stwu r1, -EXC_GENERIC_SIZE(r1)
411	stw r4, GPR4_OFFSET(r1)
412	li r4, 15
413	b ppc_exc_wrap_nopush_std
414
415	/* Symbol provided for debugging and tracing */
416	bsp_exc_vector_end:
417
418	/* Start stack area */
419	.section ".bsp_rwextra", "aw", @nobits
420	.align 4
421	.space 4096
422	start_stack_end:

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