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start.S @ b1ef3674

Last change on this file since b1ef3674 was b1ef3674, checked in by Sebastian Huber <sebastian.huber@…>, on 07/27/16 at 09:30:09

bsp/qoriq: Add QORIQ_HAS_WRITE_BACK_L1_CACHE

Fixes start via U-Boot on P1020.

Property mode set to 100644

File size: 8.3 KB

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1	/**
2	* @file
3	*
4	* @ingroup qoriq
5	*
6	* @brief BSP start.
7	*/
8
9	/*
10	* Copyright (c) 2010, 2016 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Dornierstr. 4
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.org/license/LICENSE.
21	*/
22
23	#include <rtems/score/percpu.h>
24
25	#include <bspopts.h>
26
27	#include <libcpu/powerpc-utility.h>
28
29	#include <bsp/vectors.h>
30
31	#if (QORIQ_INITIAL_MSR & MSR_FP) != 0
32	#define INITIALIZE_FPU
33	#endif
34
35	#define FIRST_TLB 0
36	#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
37	#define INITIAL_MSR r14
38	#define START_STACK r15
39	#define SAVED_LINK_REGISTER r16
40
41	.globl _start
42	#ifdef RTEMS_SMP
43	#if QORIQ_THREAD_COUNT > 1
44	.globl _start_thread
45	#endif
46	.globl _start_secondary_processor
47	#endif
48	.globl bsp_exc_vector_base
49
50	.section ".bsp_start_text", "ax"
51
52	_start:
53	bl .Linitearly
54
55	#ifdef HAS_UBOOT
56	bl bsp_uboot_copy_board_info
57	#endif /* HAS_UBOOT */
58
59	#ifdef U_BOOT_USE_FDT
60	bl bsp_fdt_copy
61	#endif /* U_BOOT_USE_FDT */
62
63	#ifdef QORIQ_HAS_WRITE_BACK_L1_CACHE
64	LWI r3, bsp_section_start_begin
65	LWI r4, bsp_section_data_load_end
66	sub r4, r4, r3
67	bl rtems_cache_flush_multiple_data_lines
68	#else
69	bl qoriq_l1cache_invalidate
70	#endif
71
72	#ifdef QORIQ_CLUSTER_1_L2CSR0
73	LWI r3, QORIQ_CLUSTER_1_L2CSR0
74	bl qoriq_l2cache_flush_invalidate
75	#endif
76
77	#ifdef QORIQ_CLUSTER_2_L2CSR0
78	LWI r3, QORIQ_CLUSTER_2_L2CSR0
79	bl qoriq_l2cache_flush_invalidate
80	#endif
81
82	#ifdef QORIQ_CLUSTER_3_L2CSR0
83	LWI r3, QORIQ_CLUSTER_3_L2CSR0
84	bl qoriq_l2cache_flush_invalidate
85	#endif
86
87	/* Get start stack */
88	LWI START_STACK, start_stack_end
89
90	bl .Linitmore
91
92	/* Copy fast text */
93	LWI r3, bsp_section_fast_text_begin
94	LWI r4, bsp_section_fast_text_load_begin
95	LWI r5, bsp_section_fast_text_size
96	bl .Lcopy
97
98	/* Copy read-only data */
99	LWI r3, bsp_section_rodata_begin
100	LWI r4, bsp_section_rodata_load_begin
101	LWI r5, bsp_section_rodata_size
102	bl .Lcopy
103
104	/* Copy fast data */
105	LWI r3, bsp_section_fast_data_begin
106	LWI r4, bsp_section_fast_data_load_begin
107	LWI r5, bsp_section_fast_data_size
108	bl .Lcopy
109
110	/* Copy data */
111	LWI r3, bsp_section_data_begin
112	LWI r4, bsp_section_data_load_begin
113	LWI r5, bsp_section_data_size
114	bl .Lcopy
115
116	/* NULL pointer access protection (only core 0 has to do this) */
117	mfspr r3, BOOKE_PIR
118	cmpwi r3, 0
119	bne .Lnull_area_setup_done
120	LWI r3, bsp_section_start_begin
121	srawi r3, r3, 2
122	mtctr r3
123	li r3, -4
124	LWI r4, 0x44000002
125	.Lnull_area_setup_loop:
126	stwu r4, 4(r3)
127	bdnz .Lnull_area_setup_loop
128	.Lnull_area_setup_done:
129
130	bl .Linitmmu
131
132	/* Clear SBSS */
133	LWI r3, bsp_section_sbss_begin
134	LWI r4, bsp_section_sbss_size
135	bl bsp_start_zero
136
137	/* Clear BSS */
138	LWI r3, bsp_section_bss_begin
139	LWI r4, bsp_section_bss_size
140	bl bsp_start_zero
141
142	/* Set up EABI and SYSV environment */
143	bl __eabi
144
145	/* Clear command line */
146	li r3, 0
147
148	bl boot_card
149
150	.Lcopy:
151	cmpw r3, r4
152	beqlr
153	b memcpy
154
155	/* Do not use r3 here, since this could be the U-Boot board info */
156	.Linitearly:
157	/* Disable decrementer */
158	mfspr r0, BOOKE_TCR
159	LWI r4, BOOKE_TCR_DIE
160	andc r0, r0, r4
161	mtspr BOOKE_TCR, r0
162
163	#ifdef QORIQ_INITIAL_SPEFSCR
164	/* SPEFSCR initialization */
165	LWI r0, QORIQ_INITIAL_SPEFSCR
166	mtspr FSL_EIS_SPEFSCR, r0
167	#endif
168
169	#ifdef QORIQ_INITIAL_BUCSR
170	/* BUCSR initialization */
171	LWI r0, QORIQ_INITIAL_BUCSR
172	mtspr FSL_EIS_BUCSR, r0
173	isync
174	#endif
175
176	#ifdef QORIQ_INITIAL_HID0
177	/* HID0 initialization */
178	LWI r0, QORIQ_INITIAL_HID0
179	mtspr HID0, r0
180	#endif
181
182	/* Invalidate TLS anchor */
183	li r2, 0
184
185	/* Set small-data anchor */
186	LA r13, _SDA_BASE_
187
188	blr
189
190	.Linitmore:
191	mflr SAVED_LINK_REGISTER
192
193	/* Invalidate all TS1 MMU entries */
194	li r3, 1
195	bl qoriq_tlb1_invalidate_all_by_ts
196
197	/* Add TS1 entry for the first 4GiB of RAM */
198	li r3, SCRATCH_TLB
199	li r4, FSL_EIS_MAS1_TS
200	li r5, FSL_EIS_MAS2_I
201	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
202	li r7, 0
203	li r8, 0
204	li r9, 11
205	bl qoriq_tlb1_write
206
207	/* MSR initialization and use TS1 for address translation */
208	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
209	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
210	mtmsr r0
211	isync
212
213	/* Initialize start stack */
214	subi r1, START_STACK, PPC_MINIMUM_STACK_FRAME_SIZE
215	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
216	li r0, 0
217	stw r0, 0(r1)
218
219	#ifdef INITIALIZE_FPU
220	bl .Linitfpu
221	#endif
222
223	mtlr SAVED_LINK_REGISTER
224	blr
225
226	.Linitmmu:
227	mflr SAVED_LINK_REGISTER
228
229	/* Configure MMU */
230	li r3, FIRST_TLB
231	li r4, SCRATCH_TLB
232	bl qoriq_mmu_config
233	mtmsr INITIAL_MSR
234	isync
235	li r3, SCRATCH_TLB
236	bl qoriq_tlb1_invalidate
237
238	mtlr SAVED_LINK_REGISTER
239	blr
240
241	#ifdef INITIALIZE_FPU
242	/*
243	* Write a value to the FPRs to initialize the hidden tag bits. See
244	* also "Core Software Initialization Requirements" of the e500mc
245	* reference manual for example.
246	*/
247	.Linitfpu:
248	li r0, 0
249	stw r0, 0(r1)
250	stw r0, 4(r1)
251	lfd f0, 0(r1)
252	fmr f1, f0
253	fmr f2, f0
254	fmr f3, f0
255	fmr f4, f0
256	fmr f5, f0
257	fmr f6, f0
258	fmr f7, f0
259	fmr f8, f0
260	fmr f9, f0
261	fmr f10, f0
262	fmr f11, f0
263	fmr f12, f0
264	fmr f13, f0
265	fmr f14, f0
266	fmr f15, f0
267	fmr f16, f0
268	fmr f17, f0
269	fmr f18, f0
270	fmr f19, f0
271	fmr f20, f0
272	fmr f21, f0
273	fmr f22, f0
274	fmr f23, f0
275	fmr f24, f0
276	fmr f25, f0
277	fmr f26, f0
278	fmr f27, f0
279	fmr f28, f0
280	fmr f29, f0
281	fmr f30, f0
282	fmr f31, f0
283	blr
284	#endif
285
286	#ifdef RTEMS_SMP
287	#if QORIQ_THREAD_COUNT > 1
288	_start_thread:
289	/* Adjust PIR */
290	mfspr r0, BOOKE_PIR
291	srawi r0, r0, 2
292	ori r0, r0, 1
293	mtspr BOOKE_PIR, r0
294
295	bl .Linitearly
296
297	/* Initialize start stack */
298	GET_SELF_CPU_CONTROL r3
299	lwz r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
300	subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
301	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
302	li r0, 0
303	stw r0, 0(r1)
304
305	#ifdef INITIALIZE_FPU
306	bl .Linitfpu
307	#endif
308
309	b qoriq_start_thread
310	#endif
311	_start_secondary_processor:
312	bl .Linitearly
313
314	/* Get start stack */
315	mr START_STACK, r3
316
317	bl .Linitmore
318	bl .Linitmmu
319	b bsp_start_on_secondary_processor
320	#endif /* RTEMS_SMP */
321
322	/* Exception vector prologues area */
323	.section ".bsp_start_text", "ax"
324	.align 4
325	bsp_exc_vector_base:
326	stw r1, ppc_exc_lock_crit@sdarel(r13)
327	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
328	li r4, -32767
329	b ppc_exc_wrap_bookE_crit
330	stwu r1, -EXC_GENERIC_SIZE(r1)
331	stw r4, GPR4_OFFSET(r1)
332	li r4, 2
333	b ppc_exc_wrap_nopush_e500_mchk
334	stwu r1, -EXC_GENERIC_SIZE(r1)
335	stw r4, GPR4_OFFSET(r1)
336	li r4, 3
337	b ppc_exc_wrap_nopush_std
338	stwu r1, -EXC_GENERIC_SIZE(r1)
339	stw r4, GPR4_OFFSET(r1)
340	li r4, 4
341	b ppc_exc_wrap_nopush_std
342	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
343	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
344	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
345	li r4, -32763
346	#endif
347	b ppc_exc_wrap_async_normal
348	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
349	nop
350	nop
351	#endif
352	stwu r1, -EXC_GENERIC_SIZE(r1)
353	stw r4, GPR4_OFFSET(r1)
354	li r4, 6
355	b ppc_exc_wrap_nopush_std
356	stwu r1, -EXC_GENERIC_SIZE(r1)
357	stw r4, GPR4_OFFSET(r1)
358	li r4, 7
359	b ppc_exc_wrap_nopush_std
360	stwu r1, -EXC_GENERIC_SIZE(r1)
361	stw r4, GPR4_OFFSET(r1)
362	li r4, 8
363	b ppc_exc_wrap_nopush_std
364	system_call:
365	stwu r1, -EXC_GENERIC_SIZE(r1)
366	stw r4, GPR4_OFFSET(r1)
367	li r4, 12
368	b ppc_exc_wrap_nopush_std
369	stwu r1, -EXC_GENERIC_SIZE(r1)
370	stw r4, GPR4_OFFSET(r1)
371	li r4, 24
372	b ppc_exc_wrap_nopush_std
373	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
374	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
375	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
376	li r4, -32752
377	#endif
378	b ppc_exc_wrap_async_normal
379	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
380	nop
381	nop
382	#endif
383	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
384	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
385	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
386	li r4, -32749
387	#endif
388	b ppc_exc_wrap_async_normal
389	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
390	nop
391	nop
392	#endif
393	stw r1, ppc_exc_lock_crit@sdarel(r13)
394	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
395	li r4, -32748
396	b ppc_exc_wrap_bookE_crit
397	stwu r1, -EXC_GENERIC_SIZE(r1)
398	stw r4, GPR4_OFFSET(r1)
399	li r4, 18
400	b ppc_exc_wrap_nopush_std
401	stwu r1, -EXC_GENERIC_SIZE(r1)
402	stw r4, GPR4_OFFSET(r1)
403	li r4, 17
404	b ppc_exc_wrap_nopush_std
405	stwu r1, -EXC_GENERIC_SIZE(r1)
406	stw r4, GPR4_OFFSET(r1)
407	li r4, 13
408	b ppc_exc_wrap_nopush_bookE_crit
409	stwu r1, -EXC_GENERIC_SIZE(r1)
410	stw r4, GPR4_OFFSET(r1)
411	li r4, 10
412	b ppc_exc_wrap_nopush_std
413	stwu r1, -EXC_GENERIC_SIZE(r1)
414	stw r4, GPR4_OFFSET(r1)
415	li r4, 25
416	b ppc_exc_wrap_nopush_std
417	stwu r1, -EXC_GENERIC_SIZE(r1)
418	stw r4, GPR4_OFFSET(r1)
419	li r4, 26
420	b ppc_exc_wrap_nopush_std
421	stwu r1, -EXC_GENERIC_SIZE(r1)
422	stw r4, GPR4_OFFSET(r1)
423	li r4, 15
424	b ppc_exc_wrap_nopush_std
425
426	/* Symbol provided for debugging and tracing */
427	bsp_exc_vector_end:
428
429	/* Start stack area */
430	.section ".bsp_rwextra", "aw", @nobits
431	.align 4
432	.space 4096
433	start_stack_end:

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