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start.S @ 50382788

Last change on this file since 50382788 was 50382788, checked in by Sebastian Huber <sebastian.huber@…>, on 07/31/17 at 13:25:12

bsps/powerpc: Add 64-bit SET_SELF_CPU_CONTROL

Update #3082.

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File size: 9.8 KB

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1	/**
2	* @file
3	*
4	* @ingroup qoriq
5	*
6	* @brief BSP start.
7	*/
8
9	/*
10	* Copyright (c) 2010, 2016 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Dornierstr. 4
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.org/license/LICENSE.
21	*/
22
23	#include <rtems/score/percpu.h>
24
25	#include <bspopts.h>
26
27	#include <libcpu/powerpc-utility.h>
28
29	#include <bsp/vectors.h>
30
31	#if (QORIQ_INITIAL_MSR & MSR_FP) != 0
32	#define INITIALIZE_FPU
33	#endif
34
35	#define FIRST_TLB 0
36	#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
37	#define INITIAL_MSR r14
38	#define START_STACK r15
39	#define SAVED_LINK_REGISTER r16
40
41	.globl _start
42	#ifdef RTEMS_SMP
43	#if QORIQ_THREAD_COUNT > 1
44	.globl _start_thread
45	#endif
46	.globl _start_secondary_processor
47	#endif
48	.globl bsp_exc_vector_base
49
50	.section ".bsp_start_text", "ax"
51
52	_start:
53	bl .Linitearly
54	bl bsp_fdt_copy
55
56	/* Get start stack */
57	LWI START_STACK, start_stack_end
58
59	bl .Linitmore
60
61	/* Copy fast text */
62	LWI r3, bsp_section_fast_text_begin
63	LWI r4, bsp_section_fast_text_load_begin
64	LWI r5, bsp_section_fast_text_size
65	bl .Lcopy
66	LWI r3, bsp_section_fast_text_begin
67	LWI r4, bsp_section_fast_text_size
68	bl rtems_cache_flush_multiple_data_lines
69
70	/* Copy read-only data */
71	LWI r3, bsp_section_rodata_begin
72	LWI r4, bsp_section_rodata_load_begin
73	LWI r5, bsp_section_rodata_size
74	bl .Lcopy
75	LWI r3, bsp_section_rodata_begin
76	LWI r4, bsp_section_rodata_size
77	bl rtems_cache_flush_multiple_data_lines
78
79	/* Copy fast data */
80	LWI r3, bsp_section_fast_data_begin
81	LWI r4, bsp_section_fast_data_load_begin
82	LWI r5, bsp_section_fast_data_size
83	bl .Lcopy
84
85	/* Copy data */
86	LWI r3, bsp_section_data_begin
87	LWI r4, bsp_section_data_load_begin
88	LWI r5, bsp_section_data_size
89	bl .Lcopy
90
91	/* NULL pointer access protection (only core 0 has to do this) */
92	mfspr r3, BOOKE_PIR
93	cmpwi r3, 0
94	bne .Lnull_area_setup_done
95	LWI r3, bsp_section_start_begin
96	srawi r3, r3, 2
97	mtctr r3
98	li r3, -4
99	LWI r4, 0x44000002
100	.Lnull_area_setup_loop:
101	stwu r4, 4(r3)
102	bdnz .Lnull_area_setup_loop
103	.Lnull_area_setup_done:
104
105	li r3, 1
106	bl .Linitmmu
107
108	/* Clear SBSS */
109	LWI r3, bsp_section_sbss_begin
110	LWI r4, bsp_section_sbss_size
111	bl bsp_start_zero
112
113	/* Clear BSS */
114	LWI r3, bsp_section_bss_begin
115	LWI r4, bsp_section_bss_size
116	bl bsp_start_zero
117
118	/* Set up EABI and SYSV environment */
119	bl __eabi
120
121	/* Clear command line */
122	li r3, 0
123
124	bl boot_card
125
126	.Lcopy:
127	cmpw r3, r4
128	beqlr
129	b memcpy
130
131	.Linitearly:
132	/*
133	* Do not use r3 here, since it holds the FDT base pointer provided by
134	* the boot loader.
135	*/
136
137	/* Disable decrementer */
138	mfspr r0, BOOKE_TCR
139	LWI r4, BOOKE_TCR_DIE
140	andc r0, r0, r4
141	mtspr BOOKE_TCR, r0
142
143	#ifdef QORIQ_INITIAL_SPEFSCR
144	/* SPEFSCR initialization */
145	LWI r0, QORIQ_INITIAL_SPEFSCR
146	mtspr FSL_EIS_SPEFSCR, r0
147	#endif
148
149	#ifdef QORIQ_INITIAL_BUCSR
150	/* BUCSR initialization */
151	LWI r0, QORIQ_INITIAL_BUCSR
152	mtspr FSL_EIS_BUCSR, r0
153	isync
154	#endif
155
156	#ifdef QORIQ_INITIAL_HID0
157	/* HID0 initialization */
158	LWI r0, QORIQ_INITIAL_HID0
159	mtspr HID0, r0
160	#endif
161
162	/* Invalidate TLS anchor */
163	li r2, 0
164
165	/* Set small-data anchor */
166	LA r13, _SDA_BASE_
167
168	SET_SELF_CPU_CONTROL r4, r5
169
170	blr
171
172	.Linitmore:
173	mflr SAVED_LINK_REGISTER
174
175	/* Invalidate all TS1 MMU entries */
176	li r3, 1
177	bl qoriq_tlb1_invalidate_all_by_ts
178
179	/* Add TS1 entry for the first 4GiB of RAM */
180	li r3, SCRATCH_TLB
181	li r4, FSL_EIS_MAS1_TS
182	li r5, FSL_EIS_MAS2_M
183	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
184	li r7, 0
185	li r8, 0
186	li r9, 11
187	bl qoriq_tlb1_write
188
189	/* MSR initialization and use TS1 for address translation */
190	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
191	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
192	mtmsr r0
193	isync
194
195	/*
196	* Initialize start stack. Make sure that we do not share a cache line
197	* with the heap block management, since initial stacks for the
198	* secondary processors are allocated from the workspace.
199	*/
200	subi r1, START_STACK, 2 * PPC_DEFAULT_CACHE_LINE_SIZE
201	clrrwi r1, r1, PPC_DEFAULT_CACHE_LINE_POWER
202	li r0, 0
203	PPC_REG_STORE r0, 0(r1)
204
205	#ifdef INITIALIZE_FPU
206	bl .Linitfpu
207	#endif
208
209	mtlr SAVED_LINK_REGISTER
210	blr
211
212	.Linitmmu:
213	mflr SAVED_LINK_REGISTER
214
215	/* Configure MMU */
216	li r4, FIRST_TLB
217	li r5, SCRATCH_TLB
218	bl qoriq_mmu_config
219	mtmsr INITIAL_MSR
220	isync
221	li r3, SCRATCH_TLB
222	bl qoriq_tlb1_invalidate
223
224	mtlr SAVED_LINK_REGISTER
225	blr
226
227	#ifdef INITIALIZE_FPU
228	/*
229	* Write a value to the FPRs to initialize the hidden tag bits. See
230	* also "Core Software Initialization Requirements" of the e500mc
231	* reference manual for example.
232	*/
233	.Linitfpu:
234	li r0, 0
235	stw r0, 0(r1)
236	stw r0, 4(r1)
237	lfd f0, 0(r1)
238	fmr f1, f0
239	fmr f2, f0
240	fmr f3, f0
241	fmr f4, f0
242	fmr f5, f0
243	fmr f6, f0
244	fmr f7, f0
245	fmr f8, f0
246	fmr f9, f0
247	fmr f10, f0
248	fmr f11, f0
249	fmr f12, f0
250	fmr f13, f0
251	fmr f14, f0
252	fmr f15, f0
253	fmr f16, f0
254	fmr f17, f0
255	fmr f18, f0
256	fmr f19, f0
257	fmr f20, f0
258	fmr f21, f0
259	fmr f22, f0
260	fmr f23, f0
261	fmr f24, f0
262	fmr f25, f0
263	fmr f26, f0
264	fmr f27, f0
265	fmr f28, f0
266	fmr f29, f0
267	fmr f30, f0
268	fmr f31, f0
269	blr
270	#endif
271
272	#ifdef RTEMS_SMP
273	#if QORIQ_THREAD_COUNT > 1
274	_start_thread:
275	/* Adjust PIR */
276	mfspr r0, BOOKE_PIR
277	srawi r0, r0, 2
278	ori r0, r0, 1
279	mtspr BOOKE_PIR, r0
280
281	bl .Linitearly
282
283	/* Initialize start stack */
284	GET_SELF_CPU_CONTROL r3
285	lwz r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
286	subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
287	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
288	li r0, 0
289	PPC_REG_STORE r0, 0(r1)
290
291	#ifdef INITIALIZE_FPU
292	bl .Linitfpu
293	#endif
294
295	b qoriq_start_thread
296	#endif
297	_start_secondary_processor:
298	bl .Linitearly
299
300	/* Get start stack */
301	mr START_STACK, r3
302
303	bl .Linitmore
304	li r3, 0
305	bl .Linitmmu
306	b bsp_start_on_secondary_processor
307	#endif /* RTEMS_SMP */
308
309	/* Exception vector prologues area */
310	.section ".bsp_start_text", "ax"
311	.align 4
312	bsp_exc_vector_base:
313	/* Critical input */
314	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
315	PPC_REG_STORE r3, GPR3_OFFSET(r1)
316	li r3, 0
317	b ppc_exc_fatal_critical
318	/* Machine check */
319	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
320	PPC_REG_STORE r3, GPR3_OFFSET(r1)
321	li r3, 1
322	b ppc_exc_fatal_machine_check
323	/* Data storage */
324	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
325	PPC_REG_STORE r3, GPR3_OFFSET(r1)
326	li r3, 2
327	b ppc_exc_fatal_normal
328	/* Instruction storage */
329	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
330	PPC_REG_STORE r3, GPR3_OFFSET(r1)
331	li r3, 3
332	b ppc_exc_fatal_normal
333	/* External input */
334	PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
335	b ppc_exc_interrupt
336	nop
337	nop
338	/* Alignment */
339	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
340	PPC_REG_STORE r3, GPR3_OFFSET(r1)
341	li r3, 5
342	b ppc_exc_fatal_normal
343	/* Program */
344	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
345	PPC_REG_STORE r3, GPR3_OFFSET(r1)
346	li r3, 6
347	b ppc_exc_fatal_normal
348	#ifdef __PPC_CPU_E6500__
349	/* Floating-point unavailable */
350	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
351	PPC_REG_STORE r3, GPR3_OFFSET(r1)
352	li r3, 7
353	b ppc_exc_fatal_normal
354	#endif
355	/* System call */
356	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
357	PPC_REG_STORE r3, GPR3_OFFSET(r1)
358	li r3, 8
359	b ppc_exc_fatal_normal
360	#ifdef __PPC_CPU_E6500__
361	/* APU unavailable */
362	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
363	PPC_REG_STORE r3, GPR3_OFFSET(r1)
364	li r3, 9
365	b ppc_exc_fatal_normal
366	#endif
367	/* Decrementer */
368	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
369	PPC_REG_STORE r3, GPR3_OFFSET(r1)
370	li r3, 10
371	b ppc_exc_fatal_normal
372	/* Fixed-interval timer interrupt */
373	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
374	PPC_REG_STORE r3, GPR3_OFFSET(r1)
375	li r3, 11
376	b ppc_exc_fatal_normal
377	/* Watchdog timer interrupt */
378	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
379	PPC_REG_STORE r3, GPR3_OFFSET(r1)
380	li r3, 12
381	b ppc_exc_fatal_critical
382	/* Data TLB error */
383	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
384	PPC_REG_STORE r3, GPR3_OFFSET(r1)
385	li r3, 13
386	b ppc_exc_fatal_normal
387	/* Instruction TLB error */
388	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
389	PPC_REG_STORE r3, GPR3_OFFSET(r1)
390	li r3, 14
391	b ppc_exc_fatal_normal
392	/* Debug */
393	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
394	PPC_REG_STORE r3, GPR3_OFFSET(r1)
395	li r3, 15
396	b ppc_exc_fatal_debug
397	/* SPE APU unavailable or AltiVec unavailable */
398	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
399	PPC_REG_STORE r3, GPR3_OFFSET(r1)
400	li r3, 32
401	b ppc_exc_fatal_normal
402	/* SPE floating-point data exception or AltiVec assist */
403	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
404	PPC_REG_STORE r3, GPR3_OFFSET(r1)
405	li r3, 33
406	b ppc_exc_fatal_normal
407	#ifndef __PPC_CPU_E6500__
408	/* SPE floating-point round exception */
409	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
410	PPC_REG_STORE r3, GPR3_OFFSET(r1)
411	li r3, 34
412	b ppc_exc_fatal_normal
413	#endif
414	/* Performance monitor */
415	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
416	PPC_REG_STORE r3, GPR3_OFFSET(r1)
417	li r3, 35
418	b ppc_exc_fatal_normal
419	#ifdef __PPC_CPU_E6500__
420	/* Processor doorbell interrupt */
421	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
422	PPC_REG_STORE r3, GPR3_OFFSET(r1)
423	li r3, 36
424	b ppc_exc_fatal_normal
425	/* Processor doorbell critical interrupt */
426	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
427	PPC_REG_STORE r3, GPR3_OFFSET(r1)
428	li r3, 37
429	b ppc_exc_fatal_critical
430	/* Guest processor doorbell */
431	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
432	PPC_REG_STORE r3, GPR3_OFFSET(r1)
433	li r3, 38
434	b ppc_exc_fatal_normal
435	/* Guest processor doorbell critical and machine check */
436	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
437	PPC_REG_STORE r3, GPR3_OFFSET(r1)
438	li r3, 39
439	b ppc_exc_fatal_critical
440	/* Hypervisor system call */
441	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
442	PPC_REG_STORE r3, GPR3_OFFSET(r1)
443	li r3, 40
444	b ppc_exc_fatal_normal
445	/* Hypervisor privilege */
446	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
447	PPC_REG_STORE r3, GPR3_OFFSET(r1)
448	li r3, 41
449	b ppc_exc_fatal_normal
450	/* LRAT error */
451	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
452	PPC_REG_STORE r3, GPR3_OFFSET(r1)
453	li r3, 42
454	b ppc_exc_fatal_normal
455	#endif
456
457	/* Symbol provided for debugging and tracing */
458	bsp_exc_vector_end:
459
460	/* Start stack area */
461	.section ".bsp_rwextra", "aw", @nobits
462	.align 4
463	.space 4096
464	start_stack_end:

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