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start.S @ 2f5e3c7

Last change on this file since 2f5e3c7 was 2f5e3c7, checked in by Sebastian Huber <sebastian.huber@…>, on 10/15/15 at 08:45:20
bsp/qoriq: Add missing isync after mtmsr
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File size: 7.9 KB

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1	/**
2	* @file
3	*
4	* @ingroup qoriq
5	*
6	* @brief BSP start.
7	*/
8
9	/*
10	* Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Dornierstr. 4
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.org/license/LICENSE.
21	*/
22
23	#include <rtems/score/percpu.h>
24
25	#include <bspopts.h>
26
27	#include <libcpu/powerpc-utility.h>
28
29	#include <bsp/vectors.h>
30
31	#if (QORIQ_INITIAL_MSR & MSR_FP) != 0
32	#define INITIALIZE_FPU
33	#endif
34
35	#define FIRST_TLB 0
36	#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
37	#define INITIAL_MSR r14
38
39	.globl _start
40	#ifdef RTEMS_SMP
41	#if QORIQ_THREAD_COUNT > 1
42	.globl _start_thread
43	#endif
44	.globl _start_secondary_processor
45	#endif
46	.globl bsp_exc_vector_base
47
48	.section ".bsp_start_text", "ax"
49
50	_start:
51	bl .Linit
52
53	#ifdef HAS_UBOOT
54	bl bsp_uboot_copy_board_info
55	#endif /* HAS_UBOOT */
56
57	/* Initial MMU setup */
58	bl qoriq_tlb1_ts_0_only
59	li r3, SCRATCH_TLB
60	li r4, FSL_EIS_MAS1_TS
61	li r5, FSL_EIS_MAS2_I
62	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
63	li r7, 0
64	li r8, 0
65	li r9, 11
66	bl qoriq_tlb1_write
67
68	/* MSR initialization */
69	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
70	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
71	mtmsr r0
72	isync
73
74	/* Initialize start stack */
75	LWI r1, start_stack_end - PPC_MINIMUM_STACK_FRAME_SIZE
76	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
77	li r0, 0
78	stw r0, 0(r1)
79
80	#ifdef INITIALIZE_FPU
81	bl .Linitfpu
82	#endif
83
84	/* Copy fast text */
85	LWI r3, bsp_section_fast_text_begin
86	LWI r4, bsp_section_fast_text_load_begin
87	LWI r5, bsp_section_fast_text_size
88	bl .Lcopy
89
90	/* Copy read-only data */
91	LWI r3, bsp_section_rodata_begin
92	LWI r4, bsp_section_rodata_load_begin
93	LWI r5, bsp_section_rodata_size
94	bl .Lcopy
95
96	/* Copy fast data */
97	LWI r3, bsp_section_fast_data_begin
98	LWI r4, bsp_section_fast_data_load_begin
99	LWI r5, bsp_section_fast_data_size
100	bl .Lcopy
101
102	/* Copy data */
103	LWI r3, bsp_section_data_begin
104	LWI r4, bsp_section_data_load_begin
105	LWI r5, bsp_section_data_size
106	bl .Lcopy
107
108	/* NULL pointer access protection (only core 0 has to do this) */
109	mfspr r3, BOOKE_PIR
110	cmpwi r3, 0
111	bne .Lnull_area_setup_done
112	LWI r3, bsp_section_start_begin
113	srawi r3, r3, 2
114	mtctr r3
115	li r3, -4
116	LWI r4, 0x44000002
117	.Lnull_area_setup_loop:
118	stwu r4, 4(r3)
119	bdnz .Lnull_area_setup_loop
120	.Lnull_area_setup_done:
121
122	/* Configure MMU */
123	li r3, FIRST_TLB
124	li r4, SCRATCH_TLB
125	bl qoriq_mmu_config
126	mtmsr INITIAL_MSR
127	isync
128	li r3, SCRATCH_TLB
129	bl qoriq_tlb1_invalidate
130
131	/* Clear SBSS */
132	LWI r3, bsp_section_sbss_begin
133	LWI r4, bsp_section_sbss_size
134	bl bsp_start_zero
135
136	/* Clear BSS */
137	LWI r3, bsp_section_bss_begin
138	LWI r4, bsp_section_bss_size
139	bl bsp_start_zero
140
141	/* Set up EABI and SYSV environment */
142	bl __eabi
143
144	/* Clear command line */
145	li r3, 0
146
147	bl boot_card
148
149	.Lcopy:
150	cmpw r3, r4
151	beqlr
152	b memcpy
153
154	/* Do not use r3 here, since this could be the U-Boot board info */
155	.Linit:
156	/* Reset time base */
157	li r0, 0
158	mtspr TBWU, r0
159	mtspr TBWL, r0
160
161	/* Disable decrementer */
162	mfspr r0, BOOKE_TCR
163	LWI r4, BOOKE_TCR_DIE
164	andc r0, r0, r4
165	mtspr BOOKE_TCR, r0
166
167	#ifdef QORIQ_INITIAL_SPEFSCR
168	/* SPEFSCR initialization */
169	LWI r0, QORIQ_INITIAL_SPEFSCR
170	mtspr FSL_EIS_SPEFSCR, r0
171	#endif
172
173	#ifdef QORIQ_INITIAL_BUCSR
174	/* BUCSR initialization */
175	LWI r0, QORIQ_INITIAL_BUCSR
176	mtspr FSL_EIS_BUCSR, r0
177	isync
178	#endif
179
180	/* Set small-data anchors */
181	LA r2, _SDA2_BASE_
182	LA r13, _SDA_BASE_
183
184	blr
185
186	#ifdef INITIALIZE_FPU
187	/*
188	* Write a value to the FPRs to initialize the hidden tag bits. See
189	* also "Core Software Initialization Requirements" of the e500mc
190	* reference manual for example.
191	*/
192	.Linitfpu:
193	li r0, 0
194	stw r0, 0(r1)
195	stw r0, 4(r1)
196	lfd f0, 0(r1)
197	fmr f1, f0
198	fmr f2, f0
199	fmr f3, f0
200	fmr f4, f0
201	fmr f5, f0
202	fmr f6, f0
203	fmr f7, f0
204	fmr f8, f0
205	fmr f9, f0
206	fmr f10, f0
207	fmr f11, f0
208	fmr f12, f0
209	fmr f13, f0
210	fmr f14, f0
211	fmr f15, f0
212	fmr f16, f0
213	fmr f17, f0
214	fmr f18, f0
215	fmr f19, f0
216	fmr f20, f0
217	fmr f21, f0
218	fmr f22, f0
219	fmr f23, f0
220	fmr f24, f0
221	fmr f25, f0
222	fmr f26, f0
223	fmr f27, f0
224	fmr f28, f0
225	fmr f29, f0
226	fmr f30, f0
227	fmr f31, f0
228	blr
229	#endif
230
231	#ifdef RTEMS_SMP
232	#if QORIQ_THREAD_COUNT > 1
233	_start_thread:
234	/* Adjust PIR */
235	mfspr r0, BOOKE_PIR
236	srawi r0, r0, 2
237	ori r0, r0, 1
238	mtspr BOOKE_PIR, r0
239
240	bl .Linit
241
242	/* Initialize start stack */
243	GET_SELF_CPU_CONTROL r3
244	lwz r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
245	subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
246	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
247	li r0, 0
248	stw r0, 0(r1)
249
250	b qoriq_start_thread
251	#endif
252	_start_secondary_processor:
253
254	bl .Linit
255
256	/* Get start stack */
257	mr r1, r3
258
259	/* Initial MMU setup */
260	bl qoriq_tlb1_ts_0_only
261	li r3, SCRATCH_TLB
262	li r4, FSL_EIS_MAS1_TS
263	li r5, FSL_EIS_MAS2_I
264	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
265	li r7, 0
266	li r8, 0
267	li r9, 11
268	bl qoriq_tlb1_write
269
270	/* MSR initialization */
271	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
272	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
273	mtmsr r0
274	isync
275
276	/* Initialize start stack */
277	subi r1, r1, PPC_MINIMUM_STACK_FRAME_SIZE
278	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
279	li r0, 0
280	stw r0, 0(r1)
281
282	#ifdef INITIALIZE_FPU
283	bl .Linitfpu
284	#endif
285
286	/* Configure MMU */
287	li r3, FIRST_TLB
288	li r4, SCRATCH_TLB
289	bl qoriq_mmu_config
290	mtmsr INITIAL_MSR
291	isync
292	li r3, SCRATCH_TLB
293	bl qoriq_tlb1_invalidate
294
295	b bsp_start_on_secondary_processor
296	#endif /* RTEMS_SMP */
297
298	/* Exception vector prologues area */
299	.section ".bsp_start_text", "ax"
300	.align 4
301	bsp_exc_vector_base:
302	stw r1, ppc_exc_lock_crit@sdarel(r13)
303	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
304	li r4, -32767
305	b ppc_exc_wrap_bookE_crit
306	stwu r1, -EXC_GENERIC_SIZE(r1)
307	stw r4, GPR4_OFFSET(r1)
308	li r4, 2
309	b ppc_exc_wrap_nopush_e500_mchk
310	stwu r1, -EXC_GENERIC_SIZE(r1)
311	stw r4, GPR4_OFFSET(r1)
312	li r4, 3
313	b ppc_exc_wrap_nopush_std
314	stwu r1, -EXC_GENERIC_SIZE(r1)
315	stw r4, GPR4_OFFSET(r1)
316	li r4, 4
317	b ppc_exc_wrap_nopush_std
318	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
319	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
320	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
321	li r4, -32763
322	#endif
323	b ppc_exc_wrap_async_normal
324	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
325	nop
326	nop
327	#endif
328	stwu r1, -EXC_GENERIC_SIZE(r1)
329	stw r4, GPR4_OFFSET(r1)
330	li r4, 6
331	b ppc_exc_wrap_nopush_std
332	stwu r1, -EXC_GENERIC_SIZE(r1)
333	stw r4, GPR4_OFFSET(r1)
334	li r4, 7
335	b ppc_exc_wrap_nopush_std
336	stwu r1, -EXC_GENERIC_SIZE(r1)
337	stw r4, GPR4_OFFSET(r1)
338	li r4, 8
339	b ppc_exc_wrap_nopush_std
340	system_call:
341	stwu r1, -EXC_GENERIC_SIZE(r1)
342	stw r4, GPR4_OFFSET(r1)
343	li r4, 12
344	b ppc_exc_wrap_nopush_std
345	stwu r1, -EXC_GENERIC_SIZE(r1)
346	stw r4, GPR4_OFFSET(r1)
347	li r4, 24
348	b ppc_exc_wrap_nopush_std
349	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
350	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
351	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
352	li r4, -32752
353	#endif
354	b ppc_exc_wrap_async_normal
355	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
356	nop
357	nop
358	#endif
359	stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
360	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
361	stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
362	li r4, -32749
363	#endif
364	b ppc_exc_wrap_async_normal
365	#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
366	nop
367	nop
368	#endif
369	stw r1, ppc_exc_lock_crit@sdarel(r13)
370	stw r4, ppc_exc_vector_register_crit@sdarel(r13)
371	li r4, -32748
372	b ppc_exc_wrap_bookE_crit
373	stwu r1, -EXC_GENERIC_SIZE(r1)
374	stw r4, GPR4_OFFSET(r1)
375	li r4, 18
376	b ppc_exc_wrap_nopush_std
377	stwu r1, -EXC_GENERIC_SIZE(r1)
378	stw r4, GPR4_OFFSET(r1)
379	li r4, 17
380	b ppc_exc_wrap_nopush_std
381	stwu r1, -EXC_GENERIC_SIZE(r1)
382	stw r4, GPR4_OFFSET(r1)
383	li r4, 13
384	b ppc_exc_wrap_nopush_bookE_crit
385	stwu r1, -EXC_GENERIC_SIZE(r1)
386	stw r4, GPR4_OFFSET(r1)
387	li r4, 10
388	b ppc_exc_wrap_nopush_std
389	stwu r1, -EXC_GENERIC_SIZE(r1)
390	stw r4, GPR4_OFFSET(r1)
391	li r4, 25
392	b ppc_exc_wrap_nopush_std
393	stwu r1, -EXC_GENERIC_SIZE(r1)
394	stw r4, GPR4_OFFSET(r1)
395	li r4, 26
396	b ppc_exc_wrap_nopush_std
397	stwu r1, -EXC_GENERIC_SIZE(r1)
398	stw r4, GPR4_OFFSET(r1)
399	li r4, 15
400	b ppc_exc_wrap_nopush_std
401
402	/* Symbol provided for debugging and tracing */
403	bsp_exc_vector_end:
404
405	/* Start stack area */
406	.section ".bsp_rwextra", "aw", @nobits
407	.align 4
408	.space 4096
409	start_stack_end:

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