source: rtems/c/src/lib/libbsp/powerpc/qoriq/irq/irq.c @ f100a58

5
Last change on this file since f100a58 was f100a58, checked in by Sebastian Huber <sebastian.huber@…>, on 09/19/17 at 12:35:02

bsp/qoriq: Add hypervisor guest SMP support

Update #3085.
  • Property mode set to 100644
File size: 9.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup QorIQ
5 *
6 * @brief Interrupt implementation.
7 */
8
9/*
10 * Copyright (c) 2010, 2017 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <sys/param.h>
24
25#include <rtems.h>
26
27#include <libcpu/powerpc-utility.h>
28
29#include <asm/epapr_hcalls.h>
30
31#include <bsp.h>
32#include <bsp/irq.h>
33#include <bsp/irq-generic.h>
34#include <bsp/vectors.h>
35#include <bsp/utility.h>
36#include <bsp/qoriq.h>
37
38#ifdef RTEMS_SMP
39#include <rtems/score/smpimpl.h>
40#endif
41
42RTEMS_INTERRUPT_LOCK_DEFINE(static, lock, "QorIQ IRQ")
43
44#define SPURIOUS 0xffff
45
46#ifdef QORIQ_IS_HYPERVISOR_GUEST
47
48void bsp_interrupt_set_affinity(
49        rtems_vector_number vector,
50        const Processor_mask *affinity
51)
52{
53        uint32_t config;
54        unsigned int priority;
55        uint32_t destination;
56        uint32_t new_destination;
57        rtems_interrupt_lock_context lock_context;
58
59        new_destination = _Processor_mask_Find_last_set(affinity) - 1;
60
61        rtems_interrupt_lock_acquire(&lock, &lock_context);
62        ev_int_get_config(vector, &config, &priority, &destination);
63        ev_int_set_config(vector, config, priority, new_destination);
64        rtems_interrupt_lock_release(&lock, &lock_context);
65}
66
67void bsp_interrupt_get_affinity(
68        rtems_vector_number vector,
69        Processor_mask *affinity
70)
71{
72        uint32_t config;
73        unsigned int priority;
74        uint32_t destination;
75
76        ev_int_get_config(vector, &config, &priority, &destination);
77        _Processor_mask_From_uint32_t(affinity, destination, 0);
78}
79
80void bsp_interrupt_vector_enable(rtems_vector_number vector)
81{
82        bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
83        ev_int_set_mask(vector, 0);
84}
85
86void bsp_interrupt_vector_disable(rtems_vector_number vector)
87{
88        bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
89        ev_int_set_mask(vector, 1);
90}
91
92void bsp_interrupt_dispatch(uintptr_t exception_number)
93{
94        unsigned int vector;
95
96        if (exception_number == 10) {
97                qoriq_decrementer_dispatch();
98                return;
99        }
100
101#ifdef RTEMS_SMP
102        if (exception_number == 36) {
103                _SMP_Inter_processor_interrupt_handler();
104                return;
105        }
106#endif
107
108        ev_int_iack(0, &vector);
109
110        if (vector != SPURIOUS) {
111                uint32_t msr;
112
113                msr = ppc_external_exceptions_enable();
114                bsp_interrupt_handler_dispatch(vector);
115                ppc_external_exceptions_disable(msr);
116
117                ev_int_eoi(vector);
118        } else {
119                bsp_interrupt_handler_default(vector);
120        }
121}
122
123rtems_status_code bsp_interrupt_facility_initialize(void)
124{
125        return RTEMS_SUCCESSFUL;
126}
127
128#else /* !QORIQ_IS_HYPERVISOR_GUEST */
129
130#define VPR_MSK BSP_BBIT32(0)
131#define VPR_A BSP_BBIT32(1)
132#define VPR_P BSP_BBIT32(8)
133#define VPR_S BSP_BBIT32(9)
134#define VPR_PRIORITY(val) BSP_BFLD32(val, 12, 15)
135#define VPR_PRIORITY_GET(reg) BSP_BFLD32GET(reg, 12, 15)
136#define VPR_PRIORITY_SET(reg, val) BSP_BFLD32SET(reg, val, 12, 15)
137#define VPR_VECTOR(val) BSP_BFLD32(val, 16, 31)
138#define VPR_VECTOR_GET(reg) BSP_BFLD32GET(reg, 16, 31)
139#define VPR_VECTOR_SET(reg, val) BSP_BFLD32SET(reg, val, 16, 31)
140
141#define GCR_RST BSP_BBIT32(0)
142#define GCR_M BSP_BBIT32(2)
143
144#define SRC_CFG_IDX(i) ((i) - QORIQ_IRQ_EXT_BASE)
145
146static const uint16_t src_cfg_offsets [] = {
147        [SRC_CFG_IDX(QORIQ_IRQ_EXT_0)] = 0x10000 >> 4,
148        [SRC_CFG_IDX(QORIQ_IRQ_EXT_1)] = 0x10020 >> 4,
149        [SRC_CFG_IDX(QORIQ_IRQ_EXT_2)] = 0x10040 >> 4,
150        [SRC_CFG_IDX(QORIQ_IRQ_EXT_3)] = 0x10060 >> 4,
151        [SRC_CFG_IDX(QORIQ_IRQ_EXT_4)] = 0x10080 >> 4,
152        [SRC_CFG_IDX(QORIQ_IRQ_EXT_5)] = 0x100a0 >> 4,
153        [SRC_CFG_IDX(QORIQ_IRQ_EXT_6)] = 0x100c0 >> 4,
154        [SRC_CFG_IDX(QORIQ_IRQ_EXT_7)] = 0x100e0 >> 4,
155        [SRC_CFG_IDX(QORIQ_IRQ_EXT_8)] = 0x10100 >> 4,
156        [SRC_CFG_IDX(QORIQ_IRQ_EXT_9)] = 0x10120 >> 4,
157        [SRC_CFG_IDX(QORIQ_IRQ_EXT_10)] = 0x10140 >> 4,
158        [SRC_CFG_IDX(QORIQ_IRQ_EXT_11)] = 0x10160 >> 4,
159        [SRC_CFG_IDX(QORIQ_IRQ_IPI_0)] = 0x010a0 >> 4,
160        [SRC_CFG_IDX(QORIQ_IRQ_IPI_1)] = 0x010b0 >> 4,
161        [SRC_CFG_IDX(QORIQ_IRQ_IPI_2)] = 0x010c0 >> 4,
162        [SRC_CFG_IDX(QORIQ_IRQ_IPI_3)] = 0x010d0 >> 4,
163        [SRC_CFG_IDX(QORIQ_IRQ_MI_0)] = 0x11600 >> 4,
164        [SRC_CFG_IDX(QORIQ_IRQ_MI_1)] = 0x11620 >> 4,
165        [SRC_CFG_IDX(QORIQ_IRQ_MI_2)] = 0x11640 >> 4,
166        [SRC_CFG_IDX(QORIQ_IRQ_MI_3)] = 0x11660 >> 4,
167        [SRC_CFG_IDX(QORIQ_IRQ_MI_4)] = 0x11680 >> 4,
168        [SRC_CFG_IDX(QORIQ_IRQ_MI_5)] = 0x116a0 >> 4,
169        [SRC_CFG_IDX(QORIQ_IRQ_MI_6)] = 0x116c0 >> 4,
170        [SRC_CFG_IDX(QORIQ_IRQ_MI_7)] = 0x116e0 >> 4,
171        [SRC_CFG_IDX(QORIQ_IRQ_MSI_0)] = 0x11c00 >> 4,
172        [SRC_CFG_IDX(QORIQ_IRQ_MSI_1)] = 0x11c20 >> 4,
173        [SRC_CFG_IDX(QORIQ_IRQ_MSI_2)] = 0x11c40 >> 4,
174        [SRC_CFG_IDX(QORIQ_IRQ_MSI_3)] = 0x11c60 >> 4,
175        [SRC_CFG_IDX(QORIQ_IRQ_MSI_4)] = 0x11c80 >> 4,
176        [SRC_CFG_IDX(QORIQ_IRQ_MSI_5)] = 0x11ca0 >> 4,
177        [SRC_CFG_IDX(QORIQ_IRQ_MSI_6)] = 0x11cc0 >> 4,
178        [SRC_CFG_IDX(QORIQ_IRQ_MSI_7)] = 0x11ce0 >> 4,
179        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_0)] = 0x01120 >> 4,
180        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_1)] = 0x01160 >> 4,
181        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_2)] = 0x011a0 >> 4,
182        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_3)] = 0x011e0 >> 4,
183        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_0)] = 0x02120 >> 4,
184        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_1)] = 0x02160 >> 4,
185        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_2)] = 0x021a0 >> 4,
186        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_3)] = 0x021e0 >> 4
187};
188
189static volatile qoriq_pic_src_cfg *get_src_cfg(rtems_vector_number vector)
190{
191        uint32_t n = MIN(RTEMS_ARRAY_SIZE(qoriq.pic.ii_0), QORIQ_IRQ_EXT_BASE);
192
193        if (vector < n) {
194                return &qoriq.pic.ii_0 [vector];
195        } else if (vector < QORIQ_IRQ_EXT_BASE) {
196                return &qoriq.pic.ii_1 [vector - n];
197        } else {
198                uintptr_t offs = ((uintptr_t)
199                        src_cfg_offsets [vector - QORIQ_IRQ_EXT_BASE]) << 4;
200
201                return (volatile qoriq_pic_src_cfg *) ((uintptr_t) &qoriq.pic + offs);
202        }
203}
204
205rtems_status_code qoriq_pic_set_priority(
206        rtems_vector_number vector,
207        int new_priority,
208        int *old_priority
209)
210{
211        rtems_status_code sc = RTEMS_SUCCESSFUL;
212        uint32_t old_vpr = 0;
213
214        if (bsp_interrupt_is_valid_vector(vector)) {
215                volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
216
217                if (QORIQ_PIC_PRIORITY_IS_VALID(new_priority)) {
218                        rtems_interrupt_lock_context lock_context;
219
220                        rtems_interrupt_lock_acquire(&lock, &lock_context);
221                        old_vpr = src_cfg->vpr;
222                        src_cfg->vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority);
223                        rtems_interrupt_lock_release(&lock, &lock_context);
224                } else if (new_priority < 0) {
225                        old_vpr = src_cfg->vpr;
226                } else {
227                        sc = RTEMS_INVALID_PRIORITY;
228                }
229        } else {
230                sc = RTEMS_INVALID_ID;
231        }
232
233        if (old_priority != NULL) {
234                *old_priority = (int) VPR_PRIORITY_GET(old_vpr);
235        }
236
237        return sc;
238}
239
240void bsp_interrupt_set_affinity(
241        rtems_vector_number vector,
242        const Processor_mask *affinity
243)
244{
245        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
246
247        src_cfg->dr = _Processor_mask_To_uint32_t(affinity, 0);
248}
249
250void bsp_interrupt_get_affinity(
251        rtems_vector_number vector,
252        Processor_mask *affinity
253)
254{
255        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
256
257        _Processor_mask_From_uint32_t(affinity, src_cfg->dr, 0);
258}
259
260static void pic_vector_enable(rtems_vector_number vector, uint32_t msk)
261{
262        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
263        rtems_interrupt_lock_context lock_context;
264
265        bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
266
267        rtems_interrupt_lock_acquire(&lock, &lock_context);
268        src_cfg->vpr = (src_cfg->vpr & ~VPR_MSK) | msk;
269        rtems_interrupt_lock_release(&lock, &lock_context);
270}
271
272void bsp_interrupt_vector_enable(rtems_vector_number vector)
273{
274        pic_vector_enable(vector, 0);
275}
276
277void bsp_interrupt_vector_disable(rtems_vector_number vector)
278{
279        pic_vector_enable(vector, VPR_MSK);
280}
281
282void bsp_interrupt_dispatch(uintptr_t exception_number)
283{
284        rtems_vector_number vector = qoriq.pic.iack;
285
286        if (vector != SPURIOUS) {
287                uint32_t msr = ppc_external_exceptions_enable();
288
289                bsp_interrupt_handler_dispatch(vector);
290
291                ppc_external_exceptions_disable(msr);
292
293                qoriq.pic.eoi = 0;
294                qoriq.pic.whoami;
295        } else {
296                bsp_interrupt_handler_default(vector);
297        }
298}
299
300static bool pic_is_ipi(rtems_vector_number vector)
301{
302        return QORIQ_IRQ_IPI_0 <= vector && vector <= QORIQ_IRQ_IPI_3;
303}
304
305static void pic_reset(void)
306{
307        qoriq.pic.gcr = GCR_RST;
308        while ((qoriq.pic.gcr & GCR_RST) != 0) {
309                /* Wait */
310        }
311}
312
313static void pic_global_timer_init(void)
314{
315        int i = 0;
316
317        qoriq.pic.tcra = 0;
318        qoriq.pic.tcrb = 0;
319
320        for (i = 0; i < 4; ++i) {
321                qoriq.pic.gta [0].bcr = GTBCR_CI;
322                qoriq.pic.gtb [0].bcr = GTBCR_CI;
323        }
324}
325
326rtems_status_code bsp_interrupt_facility_initialize(void)
327{
328        rtems_vector_number i = 0;
329        uint32_t processor_id = ppc_processor_id();
330
331        if (processor_id == 0) {
332                /* Core 0 must do the basic initialization */
333
334                pic_reset();
335
336                for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
337                        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(i);
338
339                        src_cfg->vpr = VPR_MSK | VPR_P | VPR_PRIORITY(1) | VPR_VECTOR(i);
340
341                        if (!pic_is_ipi(i)) {
342                                src_cfg->dr = 0x1;
343                        }
344                }
345
346                qoriq.pic.mer03 = 0xf;
347                qoriq.pic.mer47 = 0xf;
348                qoriq.pic.svr = SPURIOUS;
349                qoriq.pic.gcr = GCR_M;
350
351                pic_global_timer_init();
352        }
353
354        qoriq.pic.ctpr = 0;
355
356        for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
357                qoriq.pic.iack;
358                qoriq.pic.eoi = 0;
359                qoriq.pic.whoami;
360        }
361
362        return RTEMS_SUCCESSFUL;
363}
364
365#endif /* QORIQ_IS_HYPERVISOR_GUEST */
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