1 | /* include/bspopts.h.in. Generated from configure.ac by autoheader. */ |
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2 | |
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3 | /* default baud for console and other serial devices */ |
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4 | #undef BSP_CONSOLE_BAUD |
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5 | |
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6 | /* enables the data cache, if defined to a value other than zero */ |
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7 | #undef BSP_DATA_CACHE_ENABLED |
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8 | |
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9 | /* If defined, then the BSP Framework will put a non-zero pattern into the |
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10 | RTEMS Workspace and C program heap. This should assist in finding code that |
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11 | assumes memory starts set to zero. */ |
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12 | #undef BSP_DIRTY_MEMORY |
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13 | |
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14 | /* disable U-Boot work area configuration */ |
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15 | #undef BSP_DISABLE_UBOOT_WORK_AREA_CONFIG |
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16 | |
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17 | /* enables the instruction cache, if defined to a value other than zero */ |
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18 | #undef BSP_INSTRUCTION_CACHE_ENABLED |
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19 | |
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20 | /* indicate that the interrupt stack is at the work area begin */ |
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21 | #undef BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN |
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22 | |
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23 | /* If defined, print a message and wait until pressed before resetting board |
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24 | when application exits. */ |
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25 | #undef BSP_PRESS_KEY_FOR_RESET |
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26 | |
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27 | /* If defined, reset the board when the application exits. */ |
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28 | #undef BSP_RESET_BOARD_AT_EXIT |
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29 | |
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30 | /* if defined use dcbt instruction */ |
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31 | #undef BSP_USE_DATA_CACHE_BLOCK_TOUCH |
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32 | |
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33 | /* enable usage of interrupts for the UART modules */ |
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34 | #undef BSP_USE_UART_INTERRUPTS |
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35 | |
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36 | /* enables U-Boot support */ |
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37 | #undef HAS_UBOOT |
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38 | |
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39 | /* Define to the address where bug reports for this package should be sent. */ |
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40 | #undef PACKAGE_BUGREPORT |
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41 | |
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42 | /* Define to the full name of this package. */ |
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43 | #undef PACKAGE_NAME |
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44 | |
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45 | /* Define to the full name and version of this package. */ |
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46 | #undef PACKAGE_STRING |
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47 | |
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48 | /* Define to the one symbol short name of this package. */ |
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49 | #undef PACKAGE_TARNAME |
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50 | |
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51 | /* Define to the home page for this package. */ |
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52 | #undef PACKAGE_URL |
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53 | |
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54 | /* Define to the version of this package. */ |
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55 | #undef PACKAGE_VERSION |
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56 | |
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57 | /* global timer used for system clock, 0..3 maps to A0..A3, and 4..7 maps to |
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58 | B0..B3 */ |
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59 | #undef QORIQ_CLOCK_TIMER |
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60 | |
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61 | /* PHY address for eTSEC interface 1 */ |
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62 | #undef QORIQ_ETSEC_1_PHY_ADDR |
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63 | |
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64 | /* PHY address for eTSEC interface 2 */ |
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65 | #undef QORIQ_ETSEC_2_PHY_ADDR |
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66 | |
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67 | /* PHY address for eTSEC interface 3 */ |
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68 | #undef QORIQ_ETSEC_3_PHY_ADDR |
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69 | |
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70 | /* initial MSR value */ |
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71 | #undef QORIQ_INITIAL_MSR |
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72 | |
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73 | /* initial SPEFSCR value */ |
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74 | #undef QORIQ_INITIAL_SPEFSCR |
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75 | |
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76 | /* inter-processor communication area begin */ |
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77 | #undef QORIQ_INTERCOM_AREA_BEGIN |
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78 | |
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79 | /* inter-processor communication area size */ |
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80 | #undef QORIQ_INTERCOM_AREA_SIZE |
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81 | |
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82 | /* use 1 to enable UART 0, otherwise use 0 */ |
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83 | #undef QORIQ_UART_0_ENABLE |
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84 | |
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85 | /* use 1 to enable UART 1, otherwise use 0 */ |
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86 | #undef QORIQ_UART_1_ENABLE |
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87 | |
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88 | /* use 1 to enable UART 0 to Intercom bridge, otherwise use 0 */ |
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89 | #undef QORIQ_UART_BRIDGE_0_ENABLE |
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90 | |
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91 | /* use 1 to enable UART 1 to Intercom bridge, otherwise use 0 */ |
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92 | #undef QORIQ_UART_BRIDGE_1_ENABLE |
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93 | |
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94 | /* UART to Intercom bridge master core index */ |
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95 | #undef QORIQ_UART_BRIDGE_MASTER_CORE |
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96 | |
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97 | /* UART to Intercom bridge slave core index */ |
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98 | #undef QORIQ_UART_BRIDGE_SLAVE_CORE |
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99 | |
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100 | /* UART to Intercom bridge task priority */ |
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101 | #undef QORIQ_UART_BRIDGE_TASK_PRIORITY |
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