1 | /* |
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2 | * This set of routines starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before any of these are invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2008. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #include <string.h> |
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18 | #include <fcntl.h> |
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19 | #include <bsp.h> |
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20 | #include <bsp/irq.h> |
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21 | #include <bsp/bootcard.h> |
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22 | #include <rtems/libio.h> |
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23 | #include <rtems/libcsupport.h> |
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24 | #include <rtems/bspIo.h> |
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25 | #include <rtems/powerpc/powerpc.h> |
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26 | |
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27 | #include <libcpu/cpuIdent.h> |
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28 | #include <libcpu/bat.h> |
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29 | #include <libcpu/spr.h> |
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30 | |
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31 | SPR_RW(SPRG1) |
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32 | |
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33 | /* On psim, each click of the decrementer register corresponds |
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34 | * to 1 instruction. By setting this to 100, we are indicating |
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35 | * that we are assuming it can execute 100 instructions per |
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36 | * microsecond. This corresponds to sustaining 1 instruction |
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37 | * per cycle at 100 Mhz. Whether this is a good guess or not |
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38 | * is anyone's guess. |
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39 | */ |
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40 | extern int PSIM_INSTRUCTIONS_PER_MICROSECOND; |
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41 | |
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42 | /* |
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43 | * PCI Bus Frequency |
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44 | */ |
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45 | unsigned int BSP_bus_frequency; |
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46 | |
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47 | /* |
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48 | * Time base divisior (how many tick for 1 second). |
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49 | */ |
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50 | unsigned int BSP_time_base_divisor; |
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51 | |
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52 | /* |
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53 | * system init stack |
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54 | */ |
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55 | #define INIT_STACK_SIZE 0x1000 |
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56 | |
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57 | void BSP_panic(char *s) |
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58 | { |
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59 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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60 | __asm__ __volatile ("sc"); |
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61 | } |
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62 | |
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63 | void _BSP_Fatal_error(unsigned int v) |
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64 | { |
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65 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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66 | __asm__ __volatile ("sc"); |
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67 | } |
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68 | |
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69 | /* |
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70 | * This method returns the base address and size of the area which |
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71 | * is to be allocated between the RTEMS Workspace and the C Program |
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72 | * Heap. |
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73 | */ |
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74 | void bsp_get_work_area( |
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75 | void **work_area_start, |
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76 | size_t *work_area_size, |
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77 | void **heap_start, |
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78 | size_t *heap_size |
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79 | ) |
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80 | { |
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81 | *work_area_start = &end; |
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82 | *work_area_size = (void *)&RAM_END - (void *)&end; |
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83 | *heap_start = BSP_BOOTCARD_HEAP_USES_WORK_AREA; |
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84 | *heap_size = BSP_BOOTCARD_HEAP_SIZE_DEFAULT; |
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85 | } |
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86 | |
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87 | /* |
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88 | * bsp_start |
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89 | * |
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90 | * This routine does the bulk of the system initialization. |
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91 | */ |
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92 | |
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93 | void bsp_start( void ) |
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94 | { |
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95 | extern unsigned long __rtems_end[]; |
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96 | uint32_t intrStackStart; |
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97 | uint32_t intrStackSize; |
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98 | |
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99 | /* |
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100 | * Note we can not get CPU identification dynamically, so |
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101 | * force current_ppc_cpu. |
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102 | */ |
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103 | current_ppc_cpu = PPC_PSIM; |
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104 | |
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105 | /* |
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106 | * initialize the device driver parameters |
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107 | */ |
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108 | BSP_bus_frequency = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND; |
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109 | BSP_time_base_divisor = 1; |
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110 | |
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111 | /* |
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112 | * The simulator likes the exception table to be at 0xfff00000. |
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113 | */ |
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114 | |
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115 | bsp_exceptions_in_RAM = FALSE; |
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116 | |
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117 | /* |
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118 | * Initialize the interrupt related settings. |
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119 | */ |
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120 | intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE; |
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121 | intrStackSize = rtems_configuration_get_interrupt_stack_size(); |
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122 | |
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123 | /* |
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124 | * Initialize default raw exception handlers. |
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125 | */ |
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126 | ppc_exc_initialize( |
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127 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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128 | intrStackStart, |
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129 | intrStackSize |
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130 | ); |
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131 | |
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132 | /* |
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133 | * Initalize RTEMS IRQ system |
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134 | */ |
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135 | BSP_rtems_irq_mng_init(0); |
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136 | |
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137 | /* |
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138 | * Setup BATs and enable MMU |
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139 | */ |
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140 | /* Memory */ |
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141 | setdbat(0, 0x0<<24, 0x0<<24, 1<<24, _PAGE_RW); |
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142 | setibat(0, 0x0<<24, 0x0<<24, 1<<24, 0); |
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143 | /* PCI */ |
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144 | setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE); |
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145 | setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE); |
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146 | |
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147 | _write_MSR(_read_MSR() | MSR_DR | MSR_IR); |
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148 | asm volatile("sync; isync"); |
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149 | } |
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