source: rtems/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c @ af2eb77

4.104.115
Last change on this file since af2eb77 was af2eb77, checked in by Joel Sherrill <joel.sherrill@…>, on 09/19/08 at 20:40:17

2008-09-19 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, include/bsp.h, startup/bspstart.c, startup/linkcmds: Use PowerPC level shared bsp_get_work_area() implementation.
  • startup/bspgetworkarea.c: Removed.
  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 *  This set of routines starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before any of these are invoked.
6 *
7 *  COPYRIGHT (c) 1989-2008.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  $Id$
15 */
16
17#include <string.h>
18#include <fcntl.h>
19#include <bsp.h>
20#include <bsp/irq.h>
21#include <bsp/bootcard.h>
22#include <rtems/bspIo.h>
23#include <rtems/powerpc/powerpc.h>
24
25#include <libcpu/cpuIdent.h>
26#include <libcpu/bat.h>
27#include <libcpu/spr.h>
28
29SPR_RW(SPRG1)
30
31/*  On psim, each click of the decrementer register corresponds
32 *  to 1 instruction.  By setting this to 100, we are indicating
33 *  that we are assuming it can execute 100 instructions per
34 *  microsecond.  This corresponds to sustaining 1 instruction
35 *  per cycle at 100 Mhz.  Whether this is a good guess or not
36 *  is anyone's guess.
37 */
38extern int PSIM_INSTRUCTIONS_PER_MICROSECOND;
39
40/*
41 * PCI Bus Frequency
42 */
43unsigned int BSP_bus_frequency;
44
45/*
46 * Memory on this board.
47 */
48extern char RamSize[];
49uint32_t BSP_mem_size;
50
51/*
52 * Time base divisior (how many tick for 1 second).
53 */
54unsigned int BSP_time_base_divisor;
55
56void BSP_panic(char *s)
57{
58  printk("%s PANIC %s\n",_RTEMS_version, s);
59  __asm__ __volatile ("sc");
60}
61
62void _BSP_Fatal_error(unsigned int v)
63{
64  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
65  __asm__ __volatile ("sc");
66}
67
68/*
69 *  bsp_start
70 *
71 *  This routine does the bulk of the system initialization.
72 */
73
74void bsp_start( void )
75{
76  extern unsigned long __rtems_end[];
77  uint32_t intrStackStart;
78  uint32_t intrStackSize;
79
80  /*
81   * Note we can not get CPU identification dynamically, so
82   * force current_ppc_cpu.
83   */
84  current_ppc_cpu = PPC_PSIM;
85
86  /*
87   *  initialize the device driver parameters
88   */
89  BSP_bus_frequency        = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND;
90  BSP_time_base_divisor    = 1;
91
92  /*
93   *  The simulator likes the exception table to be at 0xfff00000.
94   */
95
96  bsp_exceptions_in_RAM = FALSE;
97
98  /*
99   * Initialize the interrupt related settings.
100   */
101  intrStackStart = (uint32_t) __rtems_end;
102  intrStackSize = rtems_configuration_get_interrupt_stack_size();
103
104  BSP_mem_size = RamSize;
105
106  /*
107   * Initialize default raw exception handlers.
108   */
109  ppc_exc_initialize(
110    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
111    intrStackStart,
112    intrStackSize
113  );
114
115  /*
116   * Initalize RTEMS IRQ system
117   */
118  BSP_rtems_irq_mng_init(0);
119
120  /*
121   * Setup BATs and enable MMU
122   */
123  /* Memory */
124  setdbat(0, 0x0<<24, 0x0<<24, 1<<24, _PAGE_RW);
125  setibat(0, 0x0<<24, 0x0<<24, 1<<24,        0);
126  /* PCI    */
127  setdbat(1, 0x8<<24, 0x8<<24, 1<<24,  IO_PAGE);
128  setdbat(2, 0xc<<24, 0xc<<24, 1<<24,  IO_PAGE);
129
130  _write_MSR(_read_MSR() | MSR_DR | MSR_IR);
131  asm volatile("sync; isync");
132}
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