source: rtems/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c @ 9b4422a2

4.11
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 *  This set of routines starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before any of these are invoked.
6 *
7 *  COPYRIGHT (c) 1989-2008.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 */
14
15#include <string.h>
16#include <fcntl.h>
17#include <bsp.h>
18#include <bsp/irq.h>
19#include <psim.h>
20#include <bsp/bootcard.h>
21#include <rtems/bspIo.h>
22#include <rtems/powerpc/powerpc.h>
23
24#include <libcpu/cpuIdent.h>
25#include <libcpu/bat.h>
26#include <libcpu/spr.h>
27
28SPR_RW(SPRG1)
29
30/*  On psim, each click of the decrementer register corresponds
31 *  to 1 instruction.  By setting this to 100, we are indicating
32 *  that we are assuming it can execute 100 instructions per
33 *  microsecond.  This corresponds to sustaining 1 instruction
34 *  per cycle at 100 Mhz.  Whether this is a good guess or not
35 *  is anyone's guess.
36 */
37extern int PSIM_INSTRUCTIONS_PER_MICROSECOND;
38
39/*
40 * PCI Bus Frequency
41 */
42unsigned int BSP_bus_frequency;
43
44/*
45 *  Driver configuration parameters
46 */
47uint32_t   bsp_clicks_per_usec;
48
49/*
50 * Memory on this board.
51 */
52uint32_t BSP_mem_size = (uint32_t)RamSize;
53
54/*
55 * Time base divisior (how many tick for 1 second).
56 */
57unsigned int BSP_time_base_divisor;
58
59extern unsigned long __rtems_end[];
60
61void BSP_panic(char *s)
62{
63  printk("%s PANIC %s\n",_RTEMS_version, s);
64  __asm__ __volatile ("sc");
65}
66
67void _BSP_Fatal_error(unsigned int v)
68{
69  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
70  __asm__ __volatile ("sc");
71}
72
73/*
74 *  bsp_start
75 *
76 *  This routine does the bulk of the system initialization.
77 */
78void bsp_start( void )
79{
80  rtems_status_code sc = RTEMS_SUCCESSFUL;
81  uintptr_t intrStackStart;
82  uintptr_t intrStackSize;
83
84  /*
85   * Note we can not get CPU identification dynamically.
86   * PVR has to be set to PPC_PSIM (0xfffe) from the device
87   * file.
88   */
89
90  get_ppc_cpu_type();
91
92  /*
93   *  initialize the device driver parameters
94   */
95  BSP_bus_frequency        = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND;
96  bsp_clicks_per_usec      = BSP_bus_frequency;
97  BSP_time_base_divisor    = 1;
98
99  /*
100   *  The simulator likes the exception table to be at 0xfff00000.
101   */
102  bsp_exceptions_in_RAM = FALSE;
103
104  /*
105   * Initialize the interrupt related settings.
106   */
107  intrStackStart = (uintptr_t) __rtems_end;
108  intrStackSize = rtems_configuration_get_interrupt_stack_size();
109
110  /*
111   * Initialize default raw exception handlers.
112   */
113  sc = ppc_exc_initialize(
114    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
115    intrStackStart,
116    intrStackSize
117  );
118  if (sc != RTEMS_SUCCESSFUL) {
119    BSP_panic("cannot initialize exceptions");
120  }
121
122  /*
123   * Initalize RTEMS IRQ system
124   */
125  BSP_rtems_irq_mng_init(0);
126
127  /*
128   * Setup BATs and enable MMU
129   */
130  /* Memory */
131  setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW);
132  setibat(0, 0x0<<24, 0x0<<24, 2<<24,        0);
133  /* PCI    */
134  setdbat(1, 0x8<<24, 0x8<<24, 1<<24,  IO_PAGE);
135  setdbat(2, 0xc<<24, 0xc<<24, 1<<24,  IO_PAGE);
136
137  _write_MSR(_read_MSR() | MSR_DR | MSR_IR);
138  __asm__ volatile("sync; isync");
139
140}
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