source: rtems/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c @ 001b4162

4.104.114.95
Last change on this file since 001b4162 was d4886a06, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 24, 2008 at 2:52:55 PM

Changed bsp_get_workarea() to bsp_get_work_area() and
added support for an optional separate heap area.

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 *  This set of routines starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before any of these are invoked.
6 *
7 *  COPYRIGHT (c) 1989-2008.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  $Id$
15 */
16
17#include <string.h>
18#include <fcntl.h>
19#include <bsp.h>
20#include <bsp/irq.h>
21#include <bsp/bootcard.h>
22#include <rtems/libio.h>
23#include <rtems/libcsupport.h>
24#include <rtems/bspIo.h>
25#include <rtems/powerpc/powerpc.h>
26
27#include <libcpu/cpuIdent.h>
28#include <libcpu/bat.h>
29#include <libcpu/spr.h>
30
31SPR_RW(SPRG1)
32
33/*  On psim, each click of the decrementer register corresponds
34 *  to 1 instruction.  By setting this to 100, we are indicating
35 *  that we are assuming it can execute 100 instructions per
36 *  microsecond.  This corresponds to sustaining 1 instruction
37 *  per cycle at 100 Mhz.  Whether this is a good guess or not
38 *  is anyone's guess.
39 */
40extern int PSIM_INSTRUCTIONS_PER_MICROSECOND;
41
42/*
43 * PCI Bus Frequency
44 */
45unsigned int BSP_bus_frequency;
46
47/*
48 * Time base divisior (how many tick for 1 second).
49 */
50unsigned int BSP_time_base_divisor;
51
52/*
53 * system init stack
54 */
55#define INIT_STACK_SIZE 0x1000
56
57void BSP_panic(char *s)
58{
59  printk("%s PANIC %s\n",_RTEMS_version, s);
60  __asm__ __volatile ("sc");
61}
62
63void _BSP_Fatal_error(unsigned int v)
64{
65  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
66  __asm__ __volatile ("sc");
67}
68
69/*
70 *  This method returns the base address and size of the area which
71 *  is to be allocated between the RTEMS Workspace and the C Program
72 *  Heap.
73 */
74void bsp_get_work_area(
75  void   **work_area_start,
76  size_t  *work_area_size,
77  void   **heap_start,
78  size_t  *heap_size
79)
80{
81  *work_area_start       = &end;
82  *work_area_size       = (void *)&RAM_END - (void *)&end;
83  *heap_start = BSP_BOOTCARD_HEAP_USES_WORK_AREA;
84  *heap_size = BSP_BOOTCARD_HEAP_SIZE_DEFAULT;
85}
86
87/*
88 *  bsp_start
89 *
90 *  This routine does the bulk of the system initialization.
91 */
92
93void bsp_start( void )
94{
95  extern unsigned long __rtems_end[];
96  uint32_t intrStackStart;
97  uint32_t intrStackSize;
98
99  /*
100   * Note we can not get CPU identification dynamically, so
101   * force current_ppc_cpu.
102   */
103  current_ppc_cpu = PPC_PSIM;
104
105  /*
106   *  initialize the device driver parameters
107   */
108  BSP_bus_frequency        = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND;
109  BSP_time_base_divisor    = 1;
110
111  /*
112   *  The simulator likes the exception table to be at 0xfff00000.
113   */
114
115  bsp_exceptions_in_RAM = FALSE;
116
117  /*
118   * Initialize the interrupt related settings.
119   */
120  intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
121  intrStackSize = rtems_configuration_get_interrupt_stack_size();
122
123  /*
124   * Initialize default raw exception handlers.
125   */
126  ppc_exc_initialize(
127    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
128    intrStackStart,
129    intrStackSize
130  );
131
132  /*
133   * Initalize RTEMS IRQ system
134   */
135  BSP_rtems_irq_mng_init(0);
136
137  /*
138   * Setup BATs and enable MMU
139   */
140  /* Memory */
141  setdbat(0, 0x0<<24, 0x0<<24, 1<<24, _PAGE_RW);
142  setibat(0, 0x0<<24, 0x0<<24, 1<<24,        0);
143  /* PCI    */
144  setdbat(1, 0x8<<24, 0x8<<24, 1<<24,  IO_PAGE);
145  setdbat(2, 0xc<<24, 0xc<<24, 1<<24,  IO_PAGE);
146
147  _write_MSR(_read_MSR() | MSR_DR | MSR_IR);
148  asm volatile("sync; isync");
149}
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