[52d276b6] | 1 | /* |
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| 2 | * |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * |
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| 5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in found in the file LICENSE in this distribution or at |
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| 9 | * http://www.rtems.com/license/LICENSE. |
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| 10 | * |
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| 11 | * irq.c,v 1.4.2.8 2003/09/04 18:45:20 joel Exp |
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| 12 | */ |
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| 13 | |
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| 14 | #include <rtems/system.h> |
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| 15 | #include <bsp.h> |
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| 16 | #include <bsp/irq.h> |
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| 17 | #if 0 |
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| 18 | #include <bsp/VME.h> |
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| 19 | #include <bsp/openpic.h> |
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| 20 | #endif |
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| 21 | #include <stdlib.h> |
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| 22 | |
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| 23 | #include <rtems/score/thread.h> |
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| 24 | #include <rtems/score/apiext.h> |
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| 25 | #include <libcpu/raw_exception.h> |
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| 26 | #include <libcpu/io.h> |
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| 27 | #include <bsp/vectors.h> |
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| 28 | |
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| 29 | #include <rtems/bspIo.h> /* for printk */ |
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| 30 | #define RAVEN_INTR_ACK_REG 0xfeff0030 |
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| 31 | |
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| 32 | /* |
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| 33 | * pointer to the mask representing the additionnal irq vectors |
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| 34 | * that must be disabled when a particular entry is activated. |
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| 35 | * They will be dynamically computed from teh prioruty table given |
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| 36 | * in BSP_rtems_irq_mngt_set(); |
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| 37 | * CAUTION : this table is accessed directly by interrupt routine |
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| 38 | * prologue. |
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| 39 | */ |
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| 40 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER]; |
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| 41 | /* |
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| 42 | * default handler connected on each irq after bsp initialization |
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| 43 | */ |
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| 44 | static rtems_irq_connect_data default_rtems_entry; |
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| 45 | |
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| 46 | /* |
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| 47 | * location used to store initial tables used for interrupt |
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| 48 | * management. |
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| 49 | */ |
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| 50 | static rtems_irq_global_settings* internal_config; |
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| 51 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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| 52 | |
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| 53 | /* |
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| 54 | * Check if IRQ is an ISA IRQ |
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| 55 | */ |
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| 56 | static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine) |
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| 57 | { |
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| 58 | return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) & |
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| 59 | ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET) |
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| 60 | ); |
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| 61 | } |
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| 62 | |
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| 63 | /* |
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| 64 | * Check if IRQ is an OPENPIC IRQ |
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| 65 | */ |
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| 66 | static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine) |
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| 67 | { |
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| 68 | return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) & |
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| 69 | ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET) |
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| 70 | ); |
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| 71 | } |
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| 72 | |
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| 73 | /* |
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| 74 | * Check if IRQ is a Porcessor IRQ |
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| 75 | */ |
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| 76 | static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) |
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| 77 | { |
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| 78 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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| 79 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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| 80 | ); |
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| 81 | } |
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| 82 | |
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| 83 | |
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| 84 | /* |
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| 85 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 86 | */ |
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| 87 | |
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[561f53b] | 88 | /* |
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| 89 | * Caution : this function assumes the variable "internal_config" |
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| 90 | * is already set and that the tables it contains are still valid |
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| 91 | * and accessible. |
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| 92 | */ |
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| 93 | static void compute_i8259_masks_from_prio () |
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| 94 | { |
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| 95 | int i; |
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| 96 | int j; |
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| 97 | /* |
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| 98 | * Always mask at least current interrupt to prevent re-entrance |
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| 99 | */ |
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| 100 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
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| 101 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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| 102 | for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) { |
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| 103 | /* |
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| 104 | * Mask interrupts at i8259 level that have a lower priority |
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| 105 | */ |
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| 106 | if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) { |
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| 107 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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| 108 | } |
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| 109 | } |
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| 110 | } |
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| 111 | } |
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| 112 | |
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[52d276b6] | 113 | /* |
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| 114 | * This function check that the value given for the irq line |
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| 115 | * is valid. |
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| 116 | */ |
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| 117 | |
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| 118 | static int isValidInterrupt(int irq) |
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| 119 | { |
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| 120 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) |
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| 121 | return 0; |
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| 122 | return 1; |
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| 123 | } |
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| 124 | |
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| 125 | |
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| 126 | /* |
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| 127 | * ------------------------ RTEMS Shared Irq Handler Mngt Routines ---------------- |
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| 128 | */ |
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| 129 | int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) |
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| 130 | { |
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| 131 | printk("BSP_insall_rtems_shared_irq_handler Not supported in psim\n"); |
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| 132 | return 0; |
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| 133 | } |
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| 134 | |
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| 135 | |
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| 136 | /* |
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| 137 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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| 138 | */ |
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| 139 | |
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| 140 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 141 | { |
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| 142 | unsigned int level; |
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| 143 | |
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| 144 | if (!isValidInterrupt(irq->name)) { |
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| 145 | printk("Invalid interrupt vector %d\n",irq->name); |
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| 146 | return 0; |
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| 147 | } |
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| 148 | /* |
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| 149 | * Check if default handler is actually connected. If not issue an error. |
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| 150 | * You must first get the current handler via i386_get_current_idt_entry |
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| 151 | * and then disconnect it using i386_delete_idt_entry. |
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| 152 | * RATIONALE : to always have the same transition by forcing the user |
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| 153 | * to get the previous handler before accepting to disconnect. |
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| 154 | */ |
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| 155 | _CPU_ISR_Disable(level); |
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| 156 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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| 157 | _CPU_ISR_Enable(level); |
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| 158 | printk("IRQ vector %d already connected\n",irq->name); |
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| 159 | return 0; |
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| 160 | } |
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| 161 | |
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| 162 | /* |
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| 163 | * store the data provided by user |
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| 164 | */ |
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| 165 | rtems_hdl_tbl[irq->name] = *irq; |
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| 166 | rtems_hdl_tbl[irq->name].next_handler = (void *)-1; |
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| 167 | |
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| 168 | if (is_isa_irq(irq->name)) { |
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| 169 | printk("What's a isa_irq on psim?"); |
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| 170 | } |
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| 171 | |
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| 172 | if (is_processor_irq(irq->name)) { |
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| 173 | /* |
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| 174 | * Enable exception at processor level |
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| 175 | */ |
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| 176 | } |
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| 177 | /* |
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| 178 | * Enable interrupt on device |
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| 179 | */ |
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| 180 | irq->on(irq); |
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| 181 | |
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| 182 | _CPU_ISR_Enable(level); |
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| 183 | |
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| 184 | return 1; |
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| 185 | } |
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| 186 | |
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| 187 | |
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| 188 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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| 189 | { |
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| 190 | unsigned int level; |
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| 191 | |
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| 192 | if (!isValidInterrupt(irq->name)) { |
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| 193 | return 0; |
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| 194 | } |
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| 195 | _CPU_ISR_Disable(level); |
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| 196 | *irq = rtems_hdl_tbl[irq->name]; |
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| 197 | _CPU_ISR_Enable(level); |
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| 198 | return 1; |
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| 199 | } |
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| 200 | |
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| 201 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 202 | { |
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| 203 | rtems_irq_connect_data *pchain= NULL, *vchain = NULL; |
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| 204 | unsigned int level; |
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| 205 | |
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| 206 | if (!isValidInterrupt(irq->name)) { |
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| 207 | return 0; |
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| 208 | } |
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| 209 | /* |
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| 210 | * Check if default handler is actually connected. If not issue an error. |
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| 211 | * You must first get the current handler via i386_get_current_idt_entry |
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| 212 | * and then disconnect it using i386_delete_idt_entry. |
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| 213 | * RATIONALE : to always have the same transition by forcing the user |
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| 214 | * to get the previous handler before accepting to disconnect. |
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| 215 | */ |
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| 216 | _CPU_ISR_Disable(level); |
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| 217 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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| 218 | _CPU_ISR_Enable(level); |
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| 219 | return 0; |
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| 220 | } |
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| 221 | |
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| 222 | if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 ) |
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| 223 | { |
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| 224 | int found = 0; |
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| 225 | |
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| 226 | for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]); |
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| 227 | (vchain->hdl != default_rtems_entry.hdl); |
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| 228 | (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) ) |
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| 229 | { |
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| 230 | if( vchain->hdl == irq->hdl ) |
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| 231 | { |
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| 232 | found= -1; break; |
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| 233 | } |
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| 234 | } |
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| 235 | |
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| 236 | if( !found ) |
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| 237 | { |
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| 238 | _CPU_ISR_Enable(level); |
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| 239 | return 0; |
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| 240 | } |
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| 241 | } |
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| 242 | else |
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| 243 | { |
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| 244 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) |
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| 245 | { |
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| 246 | _CPU_ISR_Enable(level); |
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| 247 | return 0; |
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| 248 | } |
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| 249 | } |
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| 250 | |
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| 251 | if (is_isa_irq(irq->name)) { |
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| 252 | printk("isa irq on psim?"); |
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| 253 | } |
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| 254 | if (is_processor_irq(irq->name)) { |
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| 255 | /* |
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| 256 | * disable exception at processor level |
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| 257 | */ |
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| 258 | } |
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| 259 | |
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| 260 | /* |
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| 261 | * Disable interrupt on device |
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| 262 | */ |
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| 263 | irq->off(irq); |
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| 264 | |
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| 265 | /* |
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| 266 | * restore the default irq value |
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| 267 | */ |
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| 268 | if( !vchain ) |
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| 269 | { |
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| 270 | /* single handler vector... */ |
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| 271 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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| 272 | } |
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| 273 | else |
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| 274 | { |
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| 275 | if( pchain ) |
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| 276 | { |
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| 277 | /* non-first handler being removed */ |
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| 278 | pchain->next_handler = vchain->next_handler; |
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| 279 | } |
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| 280 | else |
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| 281 | { |
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| 282 | /* first handler isn't malloc'ed, so just overwrite it. Since |
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| 283 | the contents of vchain are being struct copied, vchain itself |
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| 284 | goes away */ |
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| 285 | rtems_hdl_tbl[irq->name]= *vchain; |
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| 286 | } |
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| 287 | free(vchain); |
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| 288 | } |
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| 289 | |
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| 290 | _CPU_ISR_Enable(level); |
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| 291 | |
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| 292 | return 1; |
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| 293 | } |
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| 294 | |
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| 295 | /* |
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| 296 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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| 297 | */ |
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| 298 | |
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| 299 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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| 300 | { |
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| 301 | /* |
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| 302 | * Store various code accelerators |
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| 303 | */ |
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| 304 | internal_config = config; |
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| 305 | default_rtems_entry = config->defaultEntry; |
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| 306 | rtems_hdl_tbl = config->irqHdlTbl; |
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| 307 | |
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| 308 | return 1; |
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| 309 | } |
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| 310 | |
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| 311 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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| 312 | { |
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| 313 | *config = internal_config; |
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| 314 | return 0; |
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| 315 | } |
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| 316 | |
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| 317 | int _BSP_vme_bridge_irq = -1; |
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| 318 | |
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| 319 | unsigned BSP_spuriousIntr = 0; |
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| 320 | |
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| 321 | /* |
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| 322 | * High level IRQ handler called from shared_raw_irq_code_entry |
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| 323 | */ |
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| 324 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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| 325 | { |
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| 326 | register unsigned msr; |
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| 327 | register unsigned new_msr; |
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| 328 | |
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| 329 | if (excNum == ASM_DEC_VECTOR) { |
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| 330 | _CPU_MSR_GET(msr); |
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| 331 | new_msr = msr | MSR_EE; |
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| 332 | _CPU_MSR_SET(new_msr); |
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| 333 | |
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| 334 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(); |
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| 335 | |
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| 336 | _CPU_MSR_SET(msr); |
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| 337 | return; |
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| 338 | |
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| 339 | } |
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| 340 | } |
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| 341 | |
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| 342 | |
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| 343 | |
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| 344 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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| 345 | { |
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| 346 | /* |
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| 347 | * Process pending signals that have not already been |
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| 348 | * processed by _Thread_Displatch. This happens quite |
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| 349 | * unfrequently : the ISR must have posted an action |
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| 350 | * to the current running thread. |
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| 351 | */ |
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| 352 | if ( _Thread_Do_post_task_switch_extension || |
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| 353 | _Thread_Executing->do_post_task_switch_extension ) { |
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| 354 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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| 355 | _API_extensions_Run_postswitch(); |
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| 356 | } |
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| 357 | /* |
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| 358 | * I plan to process other thread related events here. |
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| 359 | * This will include DEBUG session requested from keyboard... |
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| 360 | */ |
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| 361 | } |
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