1 | /* |
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2 | * (c) 1998, Radstone Technology plc. |
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3 | * |
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4 | * |
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5 | * This is an unpublished work the copyright in which vests |
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6 | * in Radstone Technology plc. All rights reserved. |
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7 | * |
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8 | * The information contained herein is the property of Radstone |
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9 | * Technology plc. and is supplied without liability for |
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10 | * errors or omissions and no part may be reproduced, used or |
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11 | * disclosed except as authorized by contract or other written |
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12 | * permission. The copyright and the foregoing |
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13 | * restriction on reproduction, use and disclosure extend to |
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14 | * all the media in which this information may be |
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15 | * embodied. |
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16 | * |
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17 | */ |
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18 | /* vectors.s 1.1 - 95/12/04 |
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19 | * |
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20 | * This file contains the assembly code for the PowerPC |
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21 | * interrupt veneers for RTEMS. |
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22 | * |
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23 | */ |
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24 | |
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25 | /* |
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26 | * The issue with this file is getting it loaded at the right place. |
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27 | * The first vector MUST be at address 0x????0100. |
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28 | * How this is achieved is dependant on the tool chain. |
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29 | * |
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30 | * However the basic mechanism for ELF assemblers is to create a |
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31 | * section called ".vectors", which will be loaded to an address |
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32 | * between 0x????0000 and 0x????0100 (inclusive) via a link script. |
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33 | * |
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34 | * The basic mechanism for XCOFF assemblers is to place it in the |
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35 | * normal text section, and arrange for this file to be located |
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36 | * at an appropriate position on the linker command line. |
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37 | * |
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38 | * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the |
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39 | * offset from 0x????0000 to the first location in the file. This |
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40 | * will usually be 0x0000 or 0x0100. |
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41 | * |
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42 | * $Id$ |
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43 | */ |
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44 | |
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45 | #include <rtems/asm.h> |
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46 | #include "bsp.h" |
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47 | |
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48 | #ifndef PPC_VECTOR_FILE_BASE |
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49 | #error "PPC_VECTOR_FILE_BASE is not defined." |
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50 | #endif |
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51 | |
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52 | .set IP_LINK, 0 |
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53 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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54 | .set IP_0, (IP_LINK + 56) |
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55 | #else |
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56 | .set IP_0, (IP_LINK + 8) |
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57 | #endif |
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58 | .set IP_2, (IP_0 + 4) |
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59 | |
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60 | .set IP_3, (IP_2 + 4) |
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61 | .set IP_4, (IP_3 + 4) |
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62 | .set IP_5, (IP_4 + 4) |
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63 | .set IP_6, (IP_5 + 4) |
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64 | |
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65 | .set IP_7, (IP_6 + 4) |
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66 | .set IP_8, (IP_7 + 4) |
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67 | .set IP_9, (IP_8 + 4) |
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68 | .set IP_10, (IP_9 + 4) |
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69 | |
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70 | .set IP_11, (IP_10 + 4) |
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71 | .set IP_12, (IP_11 + 4) |
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72 | .set IP_13, (IP_12 + 4) |
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73 | .set IP_28, (IP_13 + 4) |
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74 | |
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75 | .set IP_29, (IP_28 + 4) |
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76 | .set IP_30, (IP_29 + 4) |
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77 | .set IP_31, (IP_30 + 4) |
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78 | .set IP_CR, (IP_31 + 4) |
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79 | |
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80 | .set IP_CTR, (IP_CR + 4) |
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81 | .set IP_XER, (IP_CTR + 4) |
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82 | .set IP_LR, (IP_XER + 4) |
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83 | .set IP_PC, (IP_LR + 4) |
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84 | |
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85 | .set IP_MSR, (IP_PC + 4) |
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86 | |
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87 | .set IP_END, (IP_MSR + 16) |
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88 | |
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89 | /* Where this file will be loaded */ |
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90 | .set file_base, PPC_VECTOR_FILE_BASE |
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91 | |
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92 | /* Vector offsets */ |
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93 | .set reset_vector,0x0100 |
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94 | .set mach_vector,0x0200 |
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95 | .set prot_vector,0x0300 |
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96 | .set isi_vector,0x0400 |
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97 | .set ext_vector,0x0500 |
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98 | .set align_vector,0x0600 |
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99 | .set prog_vector,0x0700 |
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100 | .set float_vector,0x0800 |
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101 | .set dec_vector,0x0900 |
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102 | .set sys_vector,0x00C00 |
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103 | .set trace_vector, 0x0d00 |
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104 | .set itm_vector,0x01000 |
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105 | .set dltm_vector,0x1100 |
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106 | .set dstm_vector,0x1200 |
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107 | .set addr_vector,0x1300 |
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108 | .set sysmgmt_vector,0x1400 |
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109 | |
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110 | /* Go to the right section */ |
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111 | #if PPC_ASM == PPC_ASM_ELF |
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112 | .section .vectors,"awx",@progbits |
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113 | #endif |
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114 | |
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115 | PUBLIC_VAR (__vectors) |
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116 | SYM (__vectors): |
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117 | |
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118 | #if PPCN_60X_USE_DINK |
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119 | .org reset_vector - file_base |
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120 | /* This is where the DINK soft reset handler is located */ |
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121 | ba 0xfff00180 |
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122 | |
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123 | .org mach_vector - file_base |
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124 | ba 0xfff00200 |
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125 | |
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126 | .org prot_vector - file_base |
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127 | ba 0xfff00300 |
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128 | |
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129 | .org isi_vector - file_base |
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130 | ba 0xfff00400 |
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131 | |
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132 | .org ext_vector - file_base |
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133 | rfi |
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134 | |
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135 | .org align_vector - file_base |
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136 | ba 0xfff00600 |
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137 | |
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138 | .org prog_vector - file_base |
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139 | ba 0xfff00700 |
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140 | |
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141 | .org float_vector - file_base |
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142 | ba 0xfff00800 |
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143 | |
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144 | .org dec_vector - file_base |
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145 | rfi |
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146 | |
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147 | .org sys_vector - file_base |
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148 | ba 0xfff00C00 |
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149 | |
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150 | .org trace_vector - file_base |
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151 | ba 0xfff00d00 |
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152 | |
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153 | .org itm_vector - file_base |
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154 | ba 0xfff01000 |
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155 | |
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156 | .org dltm_vector - file_base |
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157 | ba 0xfff01100 |
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158 | |
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159 | .org dstm_vector - file_base |
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160 | ba 0xfff01200 |
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161 | |
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162 | .org addr_vector - file_base |
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163 | ba 0xfff01300 |
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164 | |
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165 | .org sysmgmt_vector - file_base |
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166 | ba 0xfff01400 |
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167 | #else |
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168 | .org reset_vector - file_base |
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169 | stwu r1, -(IP_END)(r1) |
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170 | stw r4,IP_4(r1) |
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171 | li r4,1 |
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172 | display_exc: |
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173 | stw r3,IP_3(r1) |
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174 | stw r5,IP_5(r1) |
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175 | /* |
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176 | * Enable data and instruction address translation |
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177 | */ |
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178 | li r3,MSR_IR | MSR_DR |
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179 | mtmsr r3 |
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180 | lis r3,0x8000 |
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181 | stb r4,0x860(r3) |
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182 | addi r4,r4,0x30 |
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183 | waitfortx: |
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184 | lbz r5,0x3fd(r3) |
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185 | andi. r5,r5,0x20 |
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186 | beq waitfortx |
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187 | stb r4,0x3f8(r3) |
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188 | li r5,0 |
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189 | stw r4,0x00(r5) |
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190 | mfsrr0 r4 |
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191 | stw r4,0x04(r5) |
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192 | mfsrr1 r4 |
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193 | stw r4,0x08(r5) |
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194 | lwz r4,IP_4(r1) |
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195 | lwz r5,IP_5(r1) |
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196 | lwz r3,IP_3(r1) |
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197 | addi r1,r1,IP_END |
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198 | rfi |
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199 | |
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200 | .org mach_vector - file_base |
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201 | stwu r1, -(IP_END)(r1) |
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202 | stw r4,IP_4(r1) |
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203 | stw r3,IP_3(r1) |
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204 | lis r4,0 |
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205 | mfspr r3,srr0 |
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206 | stw r3,0x00(r4) |
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207 | mfspr r3,srr1 |
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208 | stw r3,0x04(r4) |
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209 | stw r5,0x08(r4) |
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210 | stw r2,0x0c(r4) |
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211 | stw r11,0x10(r4) |
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212 | stw r12,0x14(r4) |
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213 | dcbst 0,r4 |
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214 | li r4,0x02 |
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215 | b display_exc |
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216 | |
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217 | .org prot_vector - file_base |
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218 | stwu r1, -(IP_END)(r1) |
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219 | stw r4,IP_4(r1) |
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220 | li r4,0x03 |
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221 | b display_exc |
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222 | |
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223 | .org isi_vector - file_base |
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224 | stwu r1, -(IP_END)(r1) |
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225 | stw r4,IP_4(r1) |
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226 | li r4,0x04 |
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227 | b display_exc |
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228 | |
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229 | .org ext_vector - file_base |
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230 | rfi |
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231 | |
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232 | .org align_vector - file_base |
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233 | stwu r1, -(IP_END)(r1) |
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234 | stw r4,IP_4(r1) |
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235 | li r4,0x06 |
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236 | b display_exc |
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237 | |
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238 | .org prog_vector - file_base |
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239 | stwu r1, -(IP_END)(r1) |
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240 | stw r4,IP_4(r1) |
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241 | li r4,0x07 |
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242 | b display_exc |
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243 | |
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244 | .org float_vector - file_base |
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245 | stwu r1, -(IP_END)(r1) |
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246 | stw r4,IP_4(r1) |
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247 | li r4,0x08 |
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248 | b display_exc |
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249 | |
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250 | .org dec_vector - file_base |
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251 | rfi |
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252 | |
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253 | .org sys_vector - file_base |
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254 | stwu r1, -(IP_END)(r1) |
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255 | stw r4,IP_4(r1) |
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256 | li r4,0x0a |
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257 | b display_exc |
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258 | |
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259 | .org trace_vector - file_base |
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260 | stwu r1, -(IP_END)(r1) |
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261 | stw r4,IP_4(r1) |
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262 | li r4,0x0b |
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263 | b display_exc |
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264 | |
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265 | .org itm_vector - file_base |
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266 | stwu r1, -(IP_END)(r1) |
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267 | stw r4,IP_4(r1) |
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268 | li r4,0x0c |
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269 | b display_exc |
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270 | |
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271 | .org dltm_vector - file_base |
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272 | stwu r1, -(IP_END)(r1) |
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273 | stw r4,IP_4(r1) |
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274 | li r4,0x0d |
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275 | b display_exc |
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276 | |
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277 | .org dstm_vector - file_base |
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278 | stwu r1, -(IP_END)(r1) |
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279 | stw r4,IP_4(r1) |
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280 | li r4,0x0e |
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281 | b display_exc |
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282 | |
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283 | .org addr_vector - file_base |
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284 | stwu r1, -(IP_END)(r1) |
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285 | stw r4,IP_4(r1) |
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286 | li r4,0x0f |
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287 | b display_exc |
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288 | |
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289 | .org sysmgmt_vector - file_base |
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290 | stwu r1, -(IP_END)(r1) |
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291 | stw r4,IP_4(r1) |
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292 | li r4,0x00 |
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293 | b display_exc |
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294 | #endif |
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