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align_h.S @ f05b2ac

4.104.114.84.95

Last change on this file since f05b2ac was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/21/04 at 16:01:48
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1	/* align_h.s 1.1 - 95/12/04
2	*
3	* This file contains the assembly code for the PowerPC 403
4	* alignment exception handler for RTEMS.
5	*
6	* Based upon IBM provided code with the following release:
7	*
8	* This source code has been made available to you by IBM on an AS-IS
9	* basis. Anyone receiving this source is licensed under IBM
10	* copyrights to use it in any way he or she deems fit, including
11	* copying it, modifying it, compiling it, and redistributing it either
12	* with or without modifications. No license under IBM patents or
13	* patent applications is to be implied by the copyright license.
14	*
15	* Any user of this software should understand that IBM cannot provide
16	* technical support for this software and will not be responsible for
17	* any consequences resulting from the use of this software.
18	*
19	* Any person who transfers this source code or any derivative work
20	* must include the IBM copyright notice, this paragraph, and the
21	* preceding two paragraphs in the transferred software.
22	*
23	* COPYRIGHT I B M CORPORATION 1995
24	* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
25	*
26	* Modifications:
27	*
28	* Author: Andrew Bray <andy@i-cubed.co.uk>
29	*
30	* COPYRIGHT (c) 1995 by i-cubed ltd.
31	*
32	* To anyone who acknowledges that this file is provided "AS IS"
33	* without any express or implied warranty:
34	* permission to use, copy, modify, and distribute this file
35	* for any purpose is hereby granted without fee, provided that
36	* the above copyright notice and this notice appears in all
37	* copies, and that the name of i-cubed limited not be used in
38	* advertising or publicity pertaining to distribution of the
39	* software without specific, written prior permission.
40	* i-cubed limited makes no representations about the suitability
41	* of this software for any purpose.
42	*
43	* $Id$
44	*/
45
46	#include <rtems/asm.h>
47	#include "bsp.h"
48
49	.set CACHE_SIZE,16 # cache line size of 32 bytes
50	.set CACHE_SIZE_L2,4 # cache line size, log 2
51
52	.set Open_gpr0,0
53	.set Open_gpr1,4
54	.set Open_gpr2,8
55	.set Open_gpr3,12
56	.set Open_gpr4,16
57	.set Open_gpr5,20
58	.set Open_gpr6,24
59	.set Open_gpr7,28
60	.set Open_gpr8,32
61	.set Open_gpr9,36
62	.set Open_gpr10,40
63	.set Open_gpr11,44
64	.set Open_gpr12,48
65	.set Open_gpr13,52
66	.set Open_gpr14,56
67	.set Open_gpr15,60
68	.set Open_gpr16,64
69	.set Open_gpr17,68
70	.set Open_gpr18,72
71	.set Open_gpr19,76
72	.set Open_gpr20,80
73	.set Open_gpr21,84
74	.set Open_gpr22,88
75	.set Open_gpr23,92
76	.set Open_gpr24,96
77	.set Open_gpr25,100
78	.set Open_gpr26,104
79	.set Open_gpr27,108
80	.set Open_gpr28,112
81	.set Open_gpr29,116
82	.set Open_gpr30,120
83	.set Open_gpr31,124
84	.set Open_xer,128
85	.set Open_lr,132
86	.set Open_ctr,136
87	.set Open_cr,140
88	.set Open_srr2,144
89	.set Open_srr3,148
90	.set Open_srr0,152
91	.set Open_srr1,156
92
93	/*
94	* This code makes several assumptions for processing efficiency
95	* * General purpose registers are continuous in the image, beginning with
96	* Open_gpr0
97	* * Hash table is highly dependent on opcodes - opcode changes will
98	* require rework of the instruction decode mechanism.
99	*/
100
101	.text
102	.globl align_h
103
104	.align CACHE_SIZE_L2
105	align_h:
106	/*-----------------------------------------------------------------------
107	* Store GPRs in Open Reg save area
108	* Set up r2 as base reg, r1 pointing to Open Reg save area
109	----------------------------------------------------------------------/
110	stmw r0,ALIGN_REGS(r0)
111	li r1,ALIGN_REGS
112	/*-----------------------------------------------------------------------
113	* Store special purpose registers in reg save area
114	----------------------------------------------------------------------/
115	mfxer r7
116	mflr r8
117	mfcr r9
118	mfctr r10
119	stw r7,Open_xer(r1)
120	stw r8,Open_lr(r1)
121	stw r9,Open_cr(r1)
122	stw r10,Open_ctr(r1)
123	mfspr r7, srr2 /* SRR 2 */
124	mfspr r8, srr3 /* SRR 3 */
125	mfspr r9, srr0 /* SRR 0 */
126	mfspr r10, srr1 /* SRR 1 */
127	stw r7,Open_srr2(r1)
128	stw r8,Open_srr3(r1)
129	stw r9,Open_srr0(r1)
130	stw r10,Open_srr1(r1)
131
132	/* Set up common registers */
133	mfspr r5, dear /* DEAR: R5 is data exception address */
134	lwz r9,Open_srr0(r1) /* get faulting instruction */
135	addi r7,r9,4 /* bump instruction */
136	stw r7,Open_srr0(r1) /* restore to image */
137	lwz r9, 0(r9) /* retrieve actual instruction */
138	rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */
139	rlwinm r7,r9,6,26,31 /* r7 is primary opcode */
140	bl ref_point /* establish addressibility */
141	ref_point:
142	mflr r11 /* r11 is the anchor point for ref_point */
143	addi r10, r7, -31 /* r10 = r7 - 31 */
144	rlwinm r10,r10,2,2,31 /* r10 = 4 /
145	add r10, r10, r11 /* r10 += anchor point */
146	lwz r10, primary_jt-ref_point(r10)
147	mtlr r10
148	rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
149	la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
150	blr
151	primary_jt:
152	.long xform
153	.long lwz
154	.long lwzu
155	.long 0
156	.long 0
157	.long stw
158	.long stwu
159	.long 0
160	.long 0
161	.long lhz
162	.long lhzu
163	.long lha
164	.long lhau
165	.long sth
166	.long sthu
167	.long lmw
168	.long stmw
169	/*
170	* handlers
171	*/
172	/*
173	* xform instructions require an additional decode. Fortunately, a relatively
174	* simple hash step breaks the instructions out with no collisions
175	*/
176	xform:
177	rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */
178	rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */
179	add r10,r7,r10 /* r10 = r7 + r10 */
180	rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */
181	add r10,r10,r11 /* r10 += anchor point */
182	lwz r10, secondary_ht-ref_point(r10)
183	mtlr r10
184	la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
185	rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
186	blrl
187
188	secondary_ht:
189	.long lhzux /* b 0 0x137 */
190	.long lhax /* b 1 0x157 */
191	.long lhaux /* b 2 0x177 */
192	.long sthx /* b 3 0x197 */
193	.long sthux /* b 4 0x1b7 */
194	.long 0 /* b 5 */
195	.long lwbrx /* b 6 0x216 */
196	.long 0 /* b 7 */
197	.long 0 /* b 8 */
198	.long 0 /* b 9 */
199	.long stwbrx /* b A 0x296 */
200	.long 0 /* b B */
201	.long 0 /* b C */
202	.long 0 /* b D */
203	.long lhbrx /* b E 0x316 */
204	.long 0 /* b F */
205	.long 0 /* b 10 */
206	.long 0 /* b 11 */
207	.long sthbrx /* b 12 0x396 */
208	.long 0 /* b 13 */
209	.long lwarx /* b 14 0x014 */
210	.long dcbz /* b 15 0x3f6 */
211	.long 0 /* b 16 */
212	.long lwzx /* b 17 0x017 */
213	.long lwzux /* b 18 0x037 */
214	.long 0 /* b 19 */
215	.long stwcx /* b 1A 0x096 */
216	.long stwx /* b 1B 0x097 */
217	.long stwux /* b 1C 0x0B7 */
218	.long 0 /* b 1D */
219	.long 0 /* b 1E */
220	.long lhzx /* b 1F 0x117 */
221
222	/*
223	* for all handlers
224	* r4 - Addressability to interrupt context
225	* r5 - DEAR address (faulting data address)
226	* r6 - RA field * 4
227	* r7 - Address of GPR 0 in image
228	* r8 - RD field * 4
229	* r9 - Failing instruction
230	*/
231
232	/* Load halfword algebraic with update */
233	lhau:
234	/* Load halfword algebraic with update indexed */
235	lhaux:
236	stwx r5,r7,r6 /* update RA with effective addr */
237
238	/* Load halfword algebraic */
239	lha:
240	/* Load halfword algebraic indexed */
241	lhax:
242	lswi r10,r5,2 /* load two bytes into r10 */
243	srawi r10,r10,16 /* shift right 2 bytes, extending sign */
244	stwx r10,r7,r8 /* update reg image */
245	b align_complete /* return */
246
247	/* Load Half Word Byte-Reversed Indexed */
248	lhbrx:
249	lswi r10,r5,2 /* load two bytes from DEAR into r10 */
250	rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */
251	stwbrx r10,r7,r8 /* store reversed in reg image */
252	b align_complete /* return */
253
254	/* Load Half Word and Zero with Update */
255	lhzu:
256	/* Load Half Word and Zero with Update Indexed */
257	lhzux:
258	stwx r5,r7,r6 /* update RA with effective addr */
259
260	/* Load Half Word and Zero */
261	lhz:
262	/* Load Half Word and Zero Indexed */
263	lhzx:
264	lswi r10,r5,2 /* load two bytes from DEAR into r10 */
265	rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */
266	stwx r10,r7,r8 /* update reg image */
267	b align_complete /* return */
268
269	/*
270	* Load Multiple Word
271	*/
272	lmw:
273	lwzx r9,r6,r7 /* R9 contains saved value of RA */
274	addi r10,r7,324 / r10 points to r31 in image + 4 */
275	rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
276	subfic r8,r8,32 /* r8 is reg count to load */
277	mtctr r8 /* load counter */
278	addi r8,r8,-1 /* r8-- */
279	rlwinm r8,r8,2,2,31 /* r8 = 4 /
280	add r5,r5,r8 /* update DEAR to point to last reg */
281	lwmloop:
282	lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */
283	stwu r11,-4(r10) /* load image and decrement pointer */
284	addi r5,r5,-4 /* decrement effective address */
285	bdnz lwmloop
286	stwx r9,r6,r7 /* restore RA (in case it was trashed) */
287	b align_complete /* return */
288
289	/*
290	* Load Word and Reserve Indexed
291	*/
292	lwarx:
293	lswi r10,r5,4 /* load four bytes from DEAR into r10 */
294	stwx r10,r7,r8 /* update reg image */
295	rlwinm r5,r5,0,0,29 /* Word align address */
296	lwarx r10,0,r5 /* Set reservation */
297	b align_complete /* return */
298
299	/*
300	* Load Word Byte-Reversed Indexed
301	*/
302	lwbrx:
303	lswi r10,r5,4 /* load four bytes from DEAR into r10 */
304	stwbrx r10,r7,r8 /* store reversed in reg image */
305	b align_complete /* return */
306
307	/* Load Word and Zero with Update */
308	lwzu:
309	/* Load Word and Zero with Update Indexed */
310	lwzux:
311	stwx r5,r7,r6 /* update RA with effective addr */
312
313	/* Load Word and Zero */
314	lwz:
315	/* Load Word and Zero Indexed */
316	lwzx:
317	lswi r10,r5,4 /* load four bytes from DEAR into r10 */
318	stwx r10,r7,r8 /* update reg image */
319	b align_complete /* return */
320
321	/* Store instructions */
322
323	/* */
324	/* Store Half Word and Update */
325	sthu:
326	/* Store Half Word and Update Indexed */
327	sthux:
328	stwx r5,r7,r6 /* Update RA with effective address */
329
330	/* Store Half Word */
331	sth:
332	/* Store Half Word Indexed */
333	sthx:
334	lwzx r10,r8,r7 /* retrieve source register value */
335	rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */
336	stswi r10,r5,2 /* store bytes to DEAR address */
337	b align_complete /* return */
338
339	/* */
340	/* Store Half Word Byte-Reversed Indexed */
341	sthbrx:
342	lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
343	stswi r10,r5,2 /* move two bytes to DEAR address */
344	b align_complete /* return */
345
346	/* */
347	/* Store Multiple Word */
348	stmw:
349	addi r10,r7,324 / r10 points to r31 in image + 4 */
350	rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
351	subfic r8,r8,32 /* r8 is reg count to load */
352	mtctr r8 /* load counter */
353	addi r8,r8,-1 /* r8-- */
354	rlwinm r8,r8,2,2,31 /* r8 = 4 /
355	add r5,r5,r8 /* update DEAR to point to last reg */
356	stmloop:
357	lwzu r11,-4(r10) /* get register value */
358	stswi r11,r5,4 /* output to DEAR address */
359	addi r5,r5,-4 /* decrement effective address */
360	bdnz stmloop
361	b align_complete /* return */
362
363	/* */
364	/* Store Word and Update */
365	stwu:
366	/* Store Word and Update Indexed */
367	stwux:
368	stwx r5,r7,r6 /* Update RA with effective address */
369
370	/* Store Word */
371	stw:
372	/* Store Word Indexed */
373	stwx:
374	lwzx r10,r8,r7 /* retrieve source register value */
375	stswi r10,r5,4 /* store bytes to DEAR address */
376	b align_complete /* return */
377
378	/* */
379	/* Store Word Byte-Reversed Indexed */
380	stwbrx:
381	lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
382	stswi r10,r5,4 /* move two bytes to DEAR address */
383	b align_complete /* return */
384
385	/* */
386	/* Store Word Conditional Indexed */
387	stwcx:
388	rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */
389	lwz r11,0(r10) /* save original value of store */
390	stwcx. r11,r0,r10 /* attempt store to address */
391	bne stwcx_moveon /* store failed, move on */
392	stw r11,0(r10) /* repair damage */
393	lwzx r9,r7,r8 /* get register value */
394	stswi r10,r5,4 /* store bytes to DEAR address */
395	stwcx_moveon:
396	mfcr r11 /* get condition reg */
397	lwz r9,Open_cr(r1) /* get condition reg image */
398	rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */
399	lwz r11,Open_xer(r1) /* get XER reg */
400	rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */
401	stw r9,Open_cr(r1) /* store cr image */
402	b align_complete /* return */
403
404	/* */
405	/* Data Cache Block Zero */
406	dcbz:
407	rlwinm r5,r5,0,0,31-CACHE_SIZE_L2
408	/* get address to nearest Cache line */
409	addi r5,r5,-4 /* adjust by a word */
410	addi r10,r0,CACHE_SIZE/4 /* set counter value */
411	mtctr r10
412	addi r11,r0,0 /* r11 = 0 */
413	dcbz_loop:
414	stwu r11,4(r5) /* store a word and update EA */
415	bdnz dcbz_loop
416	b align_complete /* return */
417
418	align_complete:
419	/*-----------------------------------------------------------------------
420	* Restore regs and return from the interrupt
421	----------------------------------------------------------------------/
422	lmw r24,Open_xer+ALIGN_REGS(r0)
423	mtxer r24
424	mtlr r25
425	mtctr r26
426	mtcrf 0xFF, r27
427	mtspr srr2, r28 /* SRR 2 */
428	mtspr srr3, r29 /* SRR 3 */
429	mtspr srr0, r30 /* SRR 0 */
430	mtspr srr1, r31 /* SRR 1 */
431	lmw r1,Open_gpr1+ALIGN_REGS(r0)
432	lwz r0,Open_gpr0+ALIGN_REGS(r0)
433	rfi

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