[0c04c377] | 1 | /* align_h.s 1.1 - 95/12/04 |
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| 2 | * |
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| 3 | * This file contains the assembly code for the PowerPC 403 |
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| 4 | * alignment exception handler for RTEMS. |
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| 5 | * |
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| 6 | * Based upon IBM provided code with the following release: |
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| 7 | * |
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| 8 | * This source code has been made available to you by IBM on an AS-IS |
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| 9 | * basis. Anyone receiving this source is licensed under IBM |
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| 10 | * copyrights to use it in any way he or she deems fit, including |
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| 11 | * copying it, modifying it, compiling it, and redistributing it either |
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| 12 | * with or without modifications. No license under IBM patents or |
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| 13 | * patent applications is to be implied by the copyright license. |
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| 14 | * |
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| 15 | * Any user of this software should understand that IBM cannot provide |
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| 16 | * technical support for this software and will not be responsible for |
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| 17 | * any consequences resulting from the use of this software. |
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| 18 | * |
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| 19 | * Any person who transfers this source code or any derivative work |
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| 20 | * must include the IBM copyright notice, this paragraph, and the |
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| 21 | * preceding two paragraphs in the transferred software. |
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| 22 | * |
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| 23 | * COPYRIGHT I B M CORPORATION 1995 |
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| 24 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
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| 25 | * |
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| 26 | * Modifications: |
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| 27 | * |
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| 28 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 29 | * |
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| 30 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 31 | * |
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| 32 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 33 | * without any express or implied warranty: |
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| 34 | * permission to use, copy, modify, and distribute this file |
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| 35 | * for any purpose is hereby granted without fee, provided that |
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| 36 | * the above copyright notice and this notice appears in all |
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| 37 | * copies, and that the name of i-cubed limited not be used in |
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| 38 | * advertising or publicity pertaining to distribution of the |
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| 39 | * software without specific, written prior permission. |
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| 40 | * i-cubed limited makes no representations about the suitability |
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| 41 | * of this software for any purpose. |
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| 42 | * |
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| 43 | * $Id$ |
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| 44 | */ |
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| 45 | |
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| 46 | #include "asm.h" |
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| 47 | #include "bsp.h" |
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| 48 | |
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| 49 | .set CACHE_SIZE,16 # cache line size of 32 bytes |
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| 50 | .set CACHE_SIZE_L2,4 # cache line size, log 2 |
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| 51 | |
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| 52 | .set Open_gpr0,0 |
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| 53 | .set Open_gpr1,4 |
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| 54 | .set Open_gpr2,8 |
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| 55 | .set Open_gpr3,12 |
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| 56 | .set Open_gpr4,16 |
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| 57 | .set Open_gpr5,20 |
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| 58 | .set Open_gpr6,24 |
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| 59 | .set Open_gpr7,28 |
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| 60 | .set Open_gpr8,32 |
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| 61 | .set Open_gpr9,36 |
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| 62 | .set Open_gpr10,40 |
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| 63 | .set Open_gpr11,44 |
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| 64 | .set Open_gpr12,48 |
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| 65 | .set Open_gpr13,52 |
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| 66 | .set Open_gpr14,56 |
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| 67 | .set Open_gpr15,60 |
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| 68 | .set Open_gpr16,64 |
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| 69 | .set Open_gpr17,68 |
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| 70 | .set Open_gpr18,72 |
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| 71 | .set Open_gpr19,76 |
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| 72 | .set Open_gpr20,80 |
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| 73 | .set Open_gpr21,84 |
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| 74 | .set Open_gpr22,88 |
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| 75 | .set Open_gpr23,92 |
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| 76 | .set Open_gpr24,96 |
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| 77 | .set Open_gpr25,100 |
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| 78 | .set Open_gpr26,104 |
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| 79 | .set Open_gpr27,108 |
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| 80 | .set Open_gpr28,112 |
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| 81 | .set Open_gpr29,116 |
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| 82 | .set Open_gpr30,120 |
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| 83 | .set Open_gpr31,124 |
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| 84 | .set Open_xer,128 |
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| 85 | .set Open_lr,132 |
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| 86 | .set Open_ctr,136 |
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| 87 | .set Open_cr,140 |
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| 88 | .set Open_srr2,144 |
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| 89 | .set Open_srr3,148 |
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| 90 | .set Open_srr0,152 |
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| 91 | .set Open_srr1,156 |
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| 92 | |
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| 93 | |
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| 94 | /* |
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| 95 | * This code makes several assumptions for processing efficiency |
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| 96 | * * General purpose registers are continuous in the image, beginning with |
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| 97 | * Open_gpr0 |
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| 98 | * * Hash table is highly dependent on opcodes - opcode changes *will* |
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| 99 | * require rework of the instruction decode mechanism. |
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| 100 | */ |
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| 101 | |
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| 102 | .text |
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| 103 | .globl align_h |
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| 104 | |
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| 105 | .align CACHE_SIZE_L2 |
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| 106 | align_h: |
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| 107 | /*----------------------------------------------------------------------- |
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| 108 | * Store GPRs in Open Reg save area |
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| 109 | * Set up r2 as base reg, r1 pointing to Open Reg save area |
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| 110 | *----------------------------------------------------------------------*/ |
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| 111 | stmw r0,ALIGN_REGS(r0) |
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| 112 | li r1,ALIGN_REGS |
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| 113 | /*----------------------------------------------------------------------- |
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| 114 | * Store special purpose registers in reg save area |
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| 115 | *----------------------------------------------------------------------*/ |
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| 116 | mfxer r7 |
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| 117 | mflr r8 |
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| 118 | mfcr r9 |
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| 119 | mfctr r10 |
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| 120 | stw r7,Open_xer(r1) |
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| 121 | stw r8,Open_lr(r1) |
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| 122 | stw r9,Open_cr(r1) |
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| 123 | stw r10,Open_ctr(r1) |
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| 124 | mfspr r7, srr2 /* SRR 2 */ |
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| 125 | mfspr r8, srr3 /* SRR 3 */ |
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| 126 | mfspr r9, srr0 /* SRR 0 */ |
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| 127 | mfspr r10, srr1 /* SRR 1 */ |
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| 128 | stw r7,Open_srr2(r1) |
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| 129 | stw r8,Open_srr3(r1) |
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| 130 | stw r9,Open_srr0(r1) |
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| 131 | stw r10,Open_srr1(r1) |
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| 132 | |
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| 133 | /* Set up common registers */ |
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| 134 | mfspr r5, dear /* DEAR: R5 is data exception address */ |
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| 135 | lwz r9,Open_srr0(r1) /* get faulting instruction */ |
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| 136 | addi r7,r9,4 /* bump instruction */ |
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| 137 | stw r7,Open_srr0(r1) /* restore to image */ |
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| 138 | lwz r9, 0(r9) /* retrieve actual instruction */ |
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| 139 | rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */ |
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| 140 | rlwinm r7,r9,6,26,31 /* r7 is primary opcode */ |
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| 141 | bl ref_point /* establish addressibility */ |
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| 142 | ref_point: |
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| 143 | mflr r11 /* r11 is the anchor point for ref_point */ |
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| 144 | addi r10, r7, -31 /* r10 = r7 - 31 */ |
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| 145 | rlwinm r10,r10,2,2,31 /* r10 *= 4 */ |
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| 146 | add r10, r10, r11 /* r10 += anchor point */ |
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| 147 | lwz r10, primary_jt-ref_point(r10) |
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| 148 | mtlr r10 |
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| 149 | rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ |
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| 150 | la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ |
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| 151 | blr |
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| 152 | primary_jt: |
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| 153 | .long xform |
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| 154 | .long lwz |
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| 155 | .long lwzu |
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| 156 | .long 0 |
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| 157 | .long 0 |
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| 158 | .long stw |
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| 159 | .long stwu |
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| 160 | .long 0 |
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| 161 | .long 0 |
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| 162 | .long lhz |
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| 163 | .long lhzu |
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| 164 | .long lha |
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| 165 | .long lhau |
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| 166 | .long sth |
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| 167 | .long sthu |
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| 168 | .long lmw |
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| 169 | .long stmw |
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| 170 | /* |
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| 171 | * handlers |
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| 172 | */ |
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| 173 | /* |
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| 174 | * xform instructions require an additional decode. Fortunately, a relatively |
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| 175 | * simple hash step breaks the instructions out with no collisions |
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| 176 | */ |
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| 177 | xform: |
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| 178 | rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */ |
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| 179 | rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */ |
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| 180 | add r10,r7,r10 /* r10 = r7 + r10 */ |
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| 181 | rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */ |
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| 182 | add r10,r10,r11 /* r10 += anchor point */ |
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| 183 | lwz r10, secondary_ht-ref_point(r10) |
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| 184 | mtlr r10 |
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| 185 | la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ |
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| 186 | rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ |
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| 187 | blrl |
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| 188 | |
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| 189 | secondary_ht: |
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| 190 | .long lhzux /* b 0 0x137 */ |
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| 191 | .long lhax /* b 1 0x157 */ |
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| 192 | .long lhaux /* b 2 0x177 */ |
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| 193 | .long sthx /* b 3 0x197 */ |
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| 194 | .long sthux /* b 4 0x1b7 */ |
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| 195 | .long 0 /* b 5 */ |
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| 196 | .long lwbrx /* b 6 0x216 */ |
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| 197 | .long 0 /* b 7 */ |
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| 198 | .long 0 /* b 8 */ |
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| 199 | .long 0 /* b 9 */ |
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| 200 | .long stwbrx /* b A 0x296 */ |
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| 201 | .long 0 /* b B */ |
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| 202 | .long 0 /* b C */ |
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| 203 | .long 0 /* b D */ |
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| 204 | .long lhbrx /* b E 0x316 */ |
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| 205 | .long 0 /* b F */ |
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| 206 | .long 0 /* b 10 */ |
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| 207 | .long 0 /* b 11 */ |
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| 208 | .long sthbrx /* b 12 0x396 */ |
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| 209 | .long 0 /* b 13 */ |
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| 210 | .long lwarx /* b 14 0x014 */ |
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| 211 | .long dcbz /* b 15 0x3f6 */ |
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| 212 | .long 0 /* b 16 */ |
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| 213 | .long lwzx /* b 17 0x017 */ |
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| 214 | .long lwzux /* b 18 0x037 */ |
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| 215 | .long 0 /* b 19 */ |
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| 216 | .long stwcx /* b 1A 0x096 */ |
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| 217 | .long stwx /* b 1B 0x097 */ |
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| 218 | .long stwux /* b 1C 0x0B7 */ |
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| 219 | .long 0 /* b 1D */ |
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| 220 | .long 0 /* b 1E */ |
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| 221 | .long lhzx /* b 1F 0x117 */ |
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| 222 | |
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| 223 | /* |
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| 224 | * for all handlers |
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| 225 | * r4 - Addressability to interrupt context |
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| 226 | * r5 - DEAR address (faulting data address) |
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| 227 | * r6 - RA field * 4 |
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| 228 | * r7 - Address of GPR 0 in image |
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| 229 | * r8 - RD field * 4 |
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| 230 | * r9 - Failing instruction |
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| 231 | */ |
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| 232 | |
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| 233 | /* Load halfword algebraic with update */ |
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| 234 | lhau: |
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| 235 | /* Load halfword algebraic with update indexed */ |
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| 236 | lhaux: |
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| 237 | stwx r5,r7,r6 /* update RA with effective addr */ |
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| 238 | |
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| 239 | /* Load halfword algebraic */ |
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| 240 | lha: |
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| 241 | /* Load halfword algebraic indexed */ |
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| 242 | lhax: |
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| 243 | lswi r10,r5,2 /* load two bytes into r10 */ |
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| 244 | srawi r10,r10,16 /* shift right 2 bytes, extending sign */ |
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| 245 | stwx r10,r7,r8 /* update reg image */ |
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| 246 | b align_complete /* return */ |
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| 247 | |
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| 248 | /* Load Half Word Byte-Reversed Indexed */ |
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| 249 | lhbrx: |
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| 250 | lswi r10,r5,2 /* load two bytes from DEAR into r10 */ |
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| 251 | rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */ |
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| 252 | stwbrx r10,r7,r8 /* store reversed in reg image */ |
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| 253 | b align_complete /* return */ |
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| 254 | |
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| 255 | /* Load Half Word and Zero with Update */ |
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| 256 | lhzu: |
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| 257 | /* Load Half Word and Zero with Update Indexed */ |
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| 258 | lhzux: |
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| 259 | stwx r5,r7,r6 /* update RA with effective addr */ |
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| 260 | |
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| 261 | /* Load Half Word and Zero */ |
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| 262 | lhz: |
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| 263 | /* Load Half Word and Zero Indexed */ |
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| 264 | lhzx: |
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| 265 | lswi r10,r5,2 /* load two bytes from DEAR into r10 */ |
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| 266 | rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */ |
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| 267 | stwx r10,r7,r8 /* update reg image */ |
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| 268 | b align_complete /* return */ |
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| 269 | |
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| 270 | /* |
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| 271 | * Load Multiple Word |
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| 272 | */ |
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| 273 | lmw: |
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| 274 | lwzx r9,r6,r7 /* R9 contains saved value of RA */ |
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| 275 | addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ |
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| 276 | rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ |
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| 277 | subfic r8,r8,32 /* r8 is reg count to load */ |
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| 278 | mtctr r8 /* load counter */ |
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| 279 | addi r8,r8,-1 /* r8-- */ |
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| 280 | rlwinm r8,r8,2,2,31 /* r8 *= 4 */ |
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| 281 | add r5,r5,r8 /* update DEAR to point to last reg */ |
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| 282 | lwmloop: |
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| 283 | lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */ |
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| 284 | stwu r11,-4(r10) /* load image and decrement pointer */ |
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| 285 | addi r5,r5,-4 /* decrement effective address */ |
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| 286 | bdnz lwmloop |
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| 287 | stwx r9,r6,r7 /* restore RA (in case it was trashed) */ |
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| 288 | b align_complete /* return */ |
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| 289 | |
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| 290 | /* |
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| 291 | * Load Word and Reserve Indexed |
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| 292 | */ |
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| 293 | lwarx: |
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| 294 | lswi r10,r5,4 /* load four bytes from DEAR into r10 */ |
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| 295 | stwx r10,r7,r8 /* update reg image */ |
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| 296 | rlwinm r5,r5,0,0,29 /* Word align address */ |
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| 297 | lwarx r10,0,r5 /* Set reservation */ |
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| 298 | b align_complete /* return */ |
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| 299 | |
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| 300 | /* |
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| 301 | * Load Word Byte-Reversed Indexed |
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| 302 | */ |
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| 303 | lwbrx: |
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| 304 | lswi r10,r5,4 /* load four bytes from DEAR into r10 */ |
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| 305 | stwbrx r10,r7,r8 /* store reversed in reg image */ |
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| 306 | b align_complete /* return */ |
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| 307 | |
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| 308 | /* Load Word and Zero with Update */ |
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| 309 | lwzu: |
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| 310 | /* Load Word and Zero with Update Indexed */ |
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| 311 | lwzux: |
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| 312 | stwx r5,r7,r6 /* update RA with effective addr */ |
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| 313 | |
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| 314 | /* Load Word and Zero */ |
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| 315 | lwz: |
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| 316 | /* Load Word and Zero Indexed */ |
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| 317 | lwzx: |
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| 318 | lswi r10,r5,4 /* load four bytes from DEAR into r10 */ |
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| 319 | stwx r10,r7,r8 /* update reg image */ |
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| 320 | b align_complete /* return */ |
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| 321 | |
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| 322 | /* Store instructions */ |
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| 323 | |
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| 324 | /* */ |
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| 325 | /* Store Half Word and Update */ |
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| 326 | sthu: |
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| 327 | /* Store Half Word and Update Indexed */ |
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| 328 | sthux: |
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| 329 | stwx r5,r7,r6 /* Update RA with effective address */ |
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| 330 | |
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| 331 | /* Store Half Word */ |
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| 332 | sth: |
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| 333 | /* Store Half Word Indexed */ |
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| 334 | sthx: |
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| 335 | lwzx r10,r8,r7 /* retrieve source register value */ |
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| 336 | rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */ |
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| 337 | stswi r10,r5,2 /* store bytes to DEAR address */ |
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| 338 | b align_complete /* return */ |
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| 339 | |
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| 340 | /* */ |
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| 341 | /* Store Half Word Byte-Reversed Indexed */ |
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| 342 | sthbrx: |
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| 343 | lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ |
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| 344 | stswi r10,r5,2 /* move two bytes to DEAR address */ |
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| 345 | b align_complete /* return */ |
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| 346 | |
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| 347 | /* */ |
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| 348 | /* Store Multiple Word */ |
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| 349 | stmw: |
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| 350 | addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ |
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| 351 | rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ |
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| 352 | subfic r8,r8,32 /* r8 is reg count to load */ |
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| 353 | mtctr r8 /* load counter */ |
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| 354 | addi r8,r8,-1 /* r8-- */ |
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| 355 | rlwinm r8,r8,2,2,31 /* r8 *= 4 */ |
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| 356 | add r5,r5,r8 /* update DEAR to point to last reg */ |
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| 357 | stmloop: |
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| 358 | lwzu r11,-4(r10) /* get register value */ |
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| 359 | stswi r11,r5,4 /* output to DEAR address */ |
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| 360 | addi r5,r5,-4 /* decrement effective address */ |
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| 361 | bdnz stmloop |
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| 362 | b align_complete /* return */ |
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| 363 | |
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| 364 | /* */ |
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| 365 | /* Store Word and Update */ |
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| 366 | stwu: |
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| 367 | /* Store Word and Update Indexed */ |
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| 368 | stwux: |
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| 369 | stwx r5,r7,r6 /* Update RA with effective address */ |
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| 370 | |
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| 371 | /* Store Word */ |
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| 372 | stw: |
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| 373 | /* Store Word Indexed */ |
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| 374 | stwx: |
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| 375 | lwzx r10,r8,r7 /* retrieve source register value */ |
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| 376 | stswi r10,r5,4 /* store bytes to DEAR address */ |
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| 377 | b align_complete /* return */ |
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| 378 | |
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| 379 | /* */ |
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| 380 | /* Store Word Byte-Reversed Indexed */ |
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| 381 | stwbrx: |
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| 382 | lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ |
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| 383 | stswi r10,r5,4 /* move two bytes to DEAR address */ |
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| 384 | b align_complete /* return */ |
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| 385 | |
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| 386 | /* */ |
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| 387 | /* Store Word Conditional Indexed */ |
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| 388 | stwcx: |
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| 389 | rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */ |
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| 390 | lwz r11,0(r10) /* save original value of store */ |
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| 391 | stwcx. r11,r0,r10 /* attempt store to address */ |
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| 392 | bne stwcx_moveon /* store failed, move on */ |
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| 393 | stw r11,0(r10) /* repair damage */ |
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| 394 | lwzx r9,r7,r8 /* get register value */ |
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| 395 | stswi r10,r5,4 /* store bytes to DEAR address */ |
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| 396 | stwcx_moveon: |
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| 397 | mfcr r11 /* get condition reg */ |
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| 398 | lwz r9,Open_cr(r1) /* get condition reg image */ |
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| 399 | rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */ |
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| 400 | lwz r11,Open_xer(r1) /* get XER reg */ |
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| 401 | rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */ |
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| 402 | stw r9,Open_cr(r1) /* store cr image */ |
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| 403 | b align_complete /* return */ |
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| 404 | |
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| 405 | /* */ |
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| 406 | /* Data Cache Block Zero */ |
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| 407 | dcbz: |
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| 408 | rlwinm r5,r5,0,0,31-CACHE_SIZE_L2 |
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| 409 | /* get address to nearest Cache line */ |
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| 410 | addi r5,r5,-4 /* adjust by a word */ |
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| 411 | addi r10,r0,CACHE_SIZE/4 /* set counter value */ |
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| 412 | mtctr r10 |
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| 413 | addi r11,r0,0 /* r11 = 0 */ |
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| 414 | dcbz_loop: |
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| 415 | stwu r11,4(r5) /* store a word and update EA */ |
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| 416 | bdnz dcbz_loop |
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| 417 | b align_complete /* return */ |
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| 418 | |
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| 419 | align_complete: |
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| 420 | /*----------------------------------------------------------------------- |
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| 421 | * Restore regs and return from the interrupt |
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| 422 | *----------------------------------------------------------------------*/ |
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| 423 | lmw r24,Open_xer+ALIGN_REGS(r0) |
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| 424 | mtxer r24 |
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| 425 | mtlr r25 |
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| 426 | mtctr r26 |
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| 427 | mtcrf 0xFF, r27 |
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| 428 | mtspr srr2, r28 /* SRR 2 */ |
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| 429 | mtspr srr3, r29 /* SRR 3 */ |
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| 430 | mtspr srr0, r30 /* SRR 0 */ |
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| 431 | mtspr srr1, r31 /* SRR 1 */ |
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| 432 | lmw r1,Open_gpr1+ALIGN_REGS(r0) |
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| 433 | lwz r0,Open_gpr0+ALIGN_REGS(r0) |
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| 434 | rfi |
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