1 | /* |
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2 | * COPYRIGHT (c) 1998 by Radstone Technology |
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3 | * |
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4 | * |
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5 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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6 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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7 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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8 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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9 | * |
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10 | * You are hereby granted permission to use, copy, modify, and distribute |
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11 | * this file, provided that this notice, plus the above copyright notice |
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12 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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13 | * no support for this code. |
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14 | * |
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15 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #include <rtems.h> |
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22 | #include <assert.h> |
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23 | #include <stdio.h> |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <pci.h> |
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27 | |
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28 | /******************************************************************** |
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29 | ******************************************************************** |
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30 | ********* ********* |
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31 | ********* Prototypes ********* |
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32 | ********* ********* |
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33 | ******************************************************************** |
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34 | ********************************************************************/ |
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35 | |
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36 | typedef struct { |
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37 | rtems_unsigned32 PCI_ID; /* Offset 0x0000 */ |
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38 | rtems_unsigned32 PCI_CSR; /* Offset 0x0004 */ |
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39 | rtems_unsigned32 PCI_CLASS; /* Offset 0x0008 */ |
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40 | rtems_unsigned32 PCI_MISC0; /* Offset 0x000C */ |
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41 | rtems_unsigned32 PCI_BS; /* Offset 0x0010 */ |
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42 | rtems_unsigned32 Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */ |
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43 | rtems_unsigned32 PCI_MISC1; /* Offset 0x003C */ |
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44 | rtems_unsigned32 Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */ |
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45 | rtems_unsigned32 LSI0_CTL; /* Offset 0x0100 */ |
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46 | rtems_unsigned32 LSI0_BS; /* Offset 0x0104 */ |
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47 | rtems_unsigned32 LSI0_BD; /* Offset 0x0108 */ |
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48 | rtems_unsigned32 LSI0_TO; /* Offset 0x010C */ |
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49 | rtems_unsigned32 Buf_Offset_0x0110; /* Offset 0x0110 */ |
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50 | rtems_unsigned32 LSI1_CTL; /* Offset 0x0114 */ |
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51 | rtems_unsigned32 LSI1_BS; /* Offset 0x0118 */ |
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52 | rtems_unsigned32 LSI1_BD; /* Offset 0x011C */ |
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53 | rtems_unsigned32 LSI1_TO; /* Offset 0x0120 */ |
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54 | rtems_unsigned32 Buf_Offset_0x0124; /* Offset 0x0124 */ |
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55 | rtems_unsigned32 LSI2_CTL; /* Offset 0x0128 */ |
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56 | rtems_unsigned32 LSI2_BS; /* Offset 0x012C */ |
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57 | rtems_unsigned32 LSI2_BD; /* Offset 0x0130 */ |
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58 | rtems_unsigned32 LSI2_TO; /* Offset 0x0134 */ |
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59 | rtems_unsigned32 Buf_Offset_0x0138; /* Offset 0x0138 */ |
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60 | rtems_unsigned32 LSI3_CTL; /* Offset 0x013C */ |
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61 | rtems_unsigned32 LSI3_BS; /* Offset 0x0140 */ |
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62 | rtems_unsigned32 LSI3_BD; /* Offset 0x0144 */ |
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63 | rtems_unsigned32 LSI3_TO; /* Offset 0x0148 */ |
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64 | rtems_unsigned32 Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */ |
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65 | rtems_unsigned32 SCYC_CTL; /* Offset 0x0170 */ |
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66 | rtems_unsigned32 SCYC_ADDR; /* Offset 0x0174 */ |
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67 | rtems_unsigned32 SCYC_EN; /* Offset 0x0178 */ |
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68 | rtems_unsigned32 SCYC_CMP; /* Offset 0x017C */ |
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69 | rtems_unsigned32 SCYC_SWP; /* Offset 0x0180 */ |
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70 | rtems_unsigned32 LMISC; /* Offset 0x0184 */ |
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71 | rtems_unsigned32 SLSI; /* Offset 0x0188 */ |
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72 | rtems_unsigned32 L_CMDERR; /* Offset 0x018C */ |
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73 | rtems_unsigned32 LAERR; /* Offset 0x0190 */ |
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74 | rtems_unsigned32 Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */ |
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75 | rtems_unsigned32 DCTL; /* Offset 0x0200 */ |
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76 | rtems_unsigned32 DTBC; /* Offset 0x0204 */ |
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77 | rtems_unsigned32 DLA; /* Offset 0x0208 */ |
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78 | rtems_unsigned32 Buf_Offset_0x020C; /* Offset 0x020C */ |
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79 | rtems_unsigned32 DVA; /* Offset 0x0210 */ |
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80 | rtems_unsigned32 Buf_Offset_0x0214; /* Offset 0x0214 */ |
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81 | rtems_unsigned32 DCPP; /* Offset 0x0218 */ |
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82 | rtems_unsigned32 Buf_Offset_0x021C; /* Offset 0x021C */ |
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83 | rtems_unsigned32 DGCS; /* Offset 0x0220 */ |
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84 | rtems_unsigned32 D_LLUE; /* Offset 0x0224 */ |
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85 | rtems_unsigned32 Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */ |
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86 | rtems_unsigned32 LINT_EN; /* Offset 0x0300 */ |
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87 | rtems_unsigned32 LINT_STAT; /* Offset 0x0304 */ |
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88 | rtems_unsigned32 LINT_MAP0; /* Offset 0x0308 */ |
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89 | rtems_unsigned32 LINT_MAP1; /* Offset 0x030C */ |
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90 | rtems_unsigned32 VINT_EN; /* Offset 0x0310 */ |
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91 | rtems_unsigned32 VINT_STAT; /* Offset 0x0314 */ |
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92 | rtems_unsigned32 VINT_MAP0; /* Offset 0x0318 */ |
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93 | rtems_unsigned32 VINT_MAP1; /* Offset 0x031C */ |
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94 | rtems_unsigned32 STATID; /* Offset 0x0320 */ |
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95 | rtems_unsigned32 V1_STATID; /* Offset 0x0324 */ |
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96 | rtems_unsigned32 V2_STATID; /* Offset 0x0328 */ |
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97 | rtems_unsigned32 V3_STATID; /* Offset 0x032C */ |
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98 | rtems_unsigned32 V4_STATID; /* Offset 0x0330 */ |
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99 | rtems_unsigned32 V5_STATID; /* Offset 0x0334 */ |
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100 | rtems_unsigned32 V6_STATID; /* Offset 0x0338 */ |
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101 | rtems_unsigned32 V7_STATID; /* Offset 0x033C */ |
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102 | rtems_unsigned32 Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */ |
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103 | rtems_unsigned32 MAST_CTL; /* Offset 0x0400 */ |
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104 | rtems_unsigned32 MISC_CTL; /* Offset 0x0404 */ |
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105 | rtems_unsigned32 MISC_STAT; /* Offset 0x0408 */ |
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106 | rtems_unsigned32 USER_AM; /* Offset 0x040C */ |
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107 | rtems_unsigned32 Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */ |
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108 | rtems_unsigned32 VSI0_CTL; /* Offset 0x0F00 */ |
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109 | rtems_unsigned32 VSI0_BS; /* Offset 0x0F04 */ |
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110 | rtems_unsigned32 VSI0_BD; /* Offset 0x0F08 */ |
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111 | rtems_unsigned32 VSI0_TO; /* Offset 0x0F0C */ |
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112 | rtems_unsigned32 Buf_Offset_0x0f10; /* Offset 0x0F10 */ |
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113 | rtems_unsigned32 VSI1_CTL; /* Offset 0x0F14 */ |
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114 | rtems_unsigned32 VSI1_BS; /* Offset 0x0F18 */ |
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115 | rtems_unsigned32 VSI1_BD; /* Offset 0x0F1C */ |
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116 | rtems_unsigned32 VSI1_TO; /* Offset 0x0F20 */ |
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117 | rtems_unsigned32 Buf_Offset_0x0F24; /* Offset 0x0F24 */ |
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118 | rtems_unsigned32 VSI2_CTL; /* Offset 0x0F28 */ |
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119 | rtems_unsigned32 VSI2_BS; /* Offset 0x0F2C */ |
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120 | rtems_unsigned32 VSI2_BD; /* Offset 0x0F30 */ |
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121 | rtems_unsigned32 VSI2_TO; /* Offset 0x0F34 */ |
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122 | rtems_unsigned32 Buf_Offset_0x0F38; /* Offset 0x0F38 */ |
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123 | rtems_unsigned32 VSI3_CTL; /* Offset 0x0F3C */ |
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124 | rtems_unsigned32 VSI3_BS; /* Offset 0x0F40 */ |
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125 | rtems_unsigned32 VSI3_BD; /* Offset 0x0F44 */ |
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126 | rtems_unsigned32 VSI3_TO; /* Offset 0x0F48 */ |
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127 | rtems_unsigned32 Buf_Offset_0x0F4C[ 0x9 ]; /* Offset 0x0F4C */ |
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128 | rtems_unsigned32 VRAI_CTL; /* Offset 0x0F70 */ |
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129 | rtems_unsigned32 VRAI_BS; /* Offset 0x0F74 */ |
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130 | rtems_unsigned32 Buf_Offset_0x0F78[ 0x2 ]; /* Offset 0x0F78 */ |
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131 | rtems_unsigned32 VCSR_CTL; /* Offset 0x0F80 */ |
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132 | rtems_unsigned32 VCSR_TO; /* Offset 0x0F84 */ |
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133 | rtems_unsigned32 V_AMERR; /* Offset 0x0F88 */ |
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134 | rtems_unsigned32 VAERR; /* Offset 0x0F8C */ |
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135 | rtems_unsigned32 Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */ |
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136 | rtems_unsigned32 VCSR_CLR; /* Offset 0x0FF4 */ |
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137 | rtems_unsigned32 VCSR_SET; /* Offset 0x0FF8 */ |
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138 | rtems_unsigned32 VCSR_BS; /* Offset 0x0FFC */ |
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139 | } Universe_Memory; |
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140 | |
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141 | volatile Universe_Memory *UNIVERSE; |
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142 | |
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143 | /* |
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144 | * PCI_bus_write |
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145 | */ |
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146 | void PCI_bus_write( |
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147 | volatile rtems_unsigned32 * _addr, /* IN */ |
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148 | rtems_unsigned32 _data /* IN */ |
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149 | ) |
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150 | { |
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151 | outport_32(_addr, _data); |
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152 | } |
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153 | |
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154 | rtems_unsigned32 PCI_bus_read( |
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155 | volatile rtems_unsigned32 * _addr /* IN */ |
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156 | ) |
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157 | { |
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158 | rtems_unsigned32 data; |
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159 | |
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160 | inport_32(_addr, data); |
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161 | return data; |
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162 | } |
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163 | |
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164 | /******************************************************************** |
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165 | ******************************************************************** |
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166 | ********* ********* |
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167 | ********* ********* |
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168 | ********* ********* |
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169 | ******************************************************************** |
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170 | ********************************************************************/ |
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171 | |
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172 | /* |
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173 | * Initializes the UNIVERSE chip. This routine is called automatically |
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174 | * by the boot code. This routine should be called by user code only if |
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175 | * a complete PPCn_60x VME initialization is required. |
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176 | */ |
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177 | |
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178 | void InitializeUniverse() |
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179 | { |
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180 | rtems_unsigned32 pci_id; |
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181 | rtems_unsigned32 universe_temp_value; |
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182 | |
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183 | /* |
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184 | * Verify the UNIVERSE CHIP ID |
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185 | */ |
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186 | (void)PCIConfigRead32(0,4,0,PCI_CONFIG_VENDOR_LOW, &pci_id); |
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187 | |
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188 | /* |
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189 | * compare to known ID |
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190 | */ |
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191 | if (pci_id != 0x000010e3 ){ |
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192 | DEBUG_puts ("Invalid PPCN_60X_UNIVERSE_CHIP_ID: "); |
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193 | rtems_fatal_error_occurred( 0x603e0bad ); |
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194 | } |
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195 | |
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196 | (void)PCIConfigRead32(0,4,0,PCI_CONFIG_BAR_0, &universe_temp_value); |
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197 | UNIVERSE = (Universe_Memory *)(universe_temp_value & ~PCI_ADDRESS_IO_SPACE); |
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198 | |
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199 | /* |
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200 | * Set the UNIVERSE PCI Configuration Space Control and Status Register to |
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201 | * medium speed device, Target Back to Back Capable, Master Enable, Target |
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202 | * Memory Enable and Target IO Enable |
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203 | */ |
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204 | PCIConfigWrite32(0,4,0,PCI_CONFIG_COMMAND, PCI_ENABLE_IO_SPACE | |
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205 | PCI_ENABLE_MEMORY_SPACE | |
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206 | PCI_ENABLE_BUS_MASTER); |
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207 | |
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208 | /* |
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209 | * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register |
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210 | */ |
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211 | PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 ); |
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212 | |
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213 | #if 0 |
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214 | /* |
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215 | * Set VMEbus Slave Image 0 Base Address to 0x04000000 on VSI0_BS register. |
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216 | */ |
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217 | PCI_bus_write( &UNIVERSE->VSI0_BS, 0x04000000 ); |
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218 | |
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219 | /* |
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220 | * Set VMEbus Slave Image 0 Bound Address to 0x05000000 on VSI0_BD register. |
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221 | */ |
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222 | PCI_bus_write( &UNIVERSE->VSI0_BD, 0x05000000 ); |
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223 | |
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224 | /* |
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225 | * VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO |
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226 | * register. Map the VME base address 0x4000000 to local memory address 0x0 |
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227 | */ |
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228 | PCI_bus_write( &UNIVERSE->VSI0_TO, 0x7C000000 ); |
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229 | |
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230 | /* |
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231 | * Set the VMEbus Slave Image 0 Control register with write posted, |
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232 | * read prefetch and AM code set for program, data, supervisor and user mode |
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233 | */ |
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234 | PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 ); |
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235 | #endif |
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236 | |
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237 | /* |
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238 | * Set the VMEbus Master Control register with retry forever, 256 bytes |
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239 | * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes |
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240 | * aligned burst size and PCI bus number to be zero |
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241 | */ |
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242 | PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 ); |
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243 | |
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244 | /* |
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245 | * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data |
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246 | * width, A32 VMEbus Address Space, AM code to be data, none-privilleged, |
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247 | * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable |
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248 | PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 ); |
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249 | */ |
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250 | |
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251 | PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); |
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252 | PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 ); |
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253 | PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 ); |
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254 | PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 ); |
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255 | |
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256 | |
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257 | #if 0 |
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258 | /* |
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259 | * Set the PCI Slave Image 0 Control register with posted write enable, |
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260 | * 32 bit data width, A32 VMEbus address base, AM code to be data, |
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261 | * none-privilleged, single and BLT cycles on VME bus with PCI |
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262 | * bus memory space. |
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263 | PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 ); |
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264 | */ |
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265 | PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); |
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266 | |
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267 | /* |
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268 | * Set the PCI Slave Image 0 Base Address to be |
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269 | * 0x0 on LSI0_BS register. |
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270 | */ |
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271 | PCI_bus_write( &UNIVERSE->LSI0_BS, 0x00FF0000 ); |
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272 | |
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273 | /* |
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274 | * Set the PCI Slave Image 0 Bound Address to be |
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275 | * 0xFFFFF000 on VSI0_BD register. |
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276 | */ |
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277 | PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 ); |
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278 | |
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279 | /* |
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280 | * Set the PCI Slave Image 0 Translation Offset to be |
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281 | * 0x0 on VSI0_TO register. |
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282 | * Note: If the actual VME address is bigger than 0x40000000, we need |
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283 | * to set the PCI Slave Image 0 Translation Offset = 0x40000000 |
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284 | * register. |
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285 | * i.e. if actual VME ADRR = 0x50000000, then we |
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286 | * need to subtract it by 0x40000000 and set |
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287 | * the LSI0_T0 register to be 0x40000000 and then |
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288 | * perform a PCI data access by adding 0xC0000000 to |
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289 | * 0x10000000 -- which is came form the result of |
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290 | * (0x50000000 - 0x40000000). |
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291 | */ |
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292 | PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 ); |
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293 | #endif |
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294 | |
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295 | /* |
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296 | * Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of |
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297 | * BI-Mode VMEbus accesses can be made. |
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298 | */ |
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299 | |
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300 | universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL ); |
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301 | |
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302 | if (universe_temp_value & 0x100000) |
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303 | PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF)); |
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304 | } |
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305 | |
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306 | /* |
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307 | * Set the slave VME base address to the specified base address. |
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308 | * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus |
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309 | * Slave Image 0 registers. |
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310 | */ |
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311 | void set_vme_base_address ( |
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312 | rtems_unsigned32 base_address |
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313 | ) |
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314 | { |
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315 | volatile rtems_unsigned32 temp; |
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316 | |
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317 | /* |
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318 | * Calculate the current size of the Slave VME image 0 |
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319 | */ |
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320 | temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - |
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321 | ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000); |
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322 | |
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323 | /* |
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324 | * Set the VMEbus Slave Image 0 Base Address to be |
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325 | * the specifed base address on VSI0_BS register. |
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326 | */ |
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327 | PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) ); |
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328 | |
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329 | /* |
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330 | * Update the VMEbus Slave Image 0 Bound Address. |
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331 | */ |
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332 | PCI_bus_write( &UNIVERSE->VSI0_BD, temp ); |
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333 | |
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334 | /* |
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335 | * Update the VMEbus Slave Image 0 Translation Offset |
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336 | */ |
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337 | temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000; |
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338 | PCI_bus_write( &UNIVERSE->VSI0_TO, temp ); |
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339 | } |
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340 | |
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341 | /* |
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342 | * Gets the VME base address |
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343 | */ |
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344 | rtems_unsigned32 get_vme_base_address () |
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345 | { |
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346 | volatile rtems_unsigned32 temp; |
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347 | |
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348 | temp = PCI_bus_read( &UNIVERSE->VSI0_BS ); |
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349 | temp &= 0xFFFFF000; |
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350 | return (temp); |
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351 | } |
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352 | |
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353 | rtems_unsigned32 get_vme_slave_size() |
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354 | { |
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355 | volatile rtems_unsigned32 temp; |
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356 | temp = PCI_bus_read( &UNIVERSE->VSI0_BD); |
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357 | temp &= 0xFFFFF000; |
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358 | temp = temp - get_vme_base_address (); |
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359 | return temp; |
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360 | } |
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361 | |
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362 | /* |
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363 | * Set the size of the VME slave image |
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364 | * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) |
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365 | */ |
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366 | void set_vme_slave_size (rtems_unsigned32 size) |
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367 | { |
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368 | volatile rtems_unsigned32 temp; |
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369 | |
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370 | if (size<0) |
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371 | size = 0; |
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372 | |
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373 | if (size > 0x17FFFFF) |
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374 | size = 0x17FFFFF; |
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375 | |
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376 | /* |
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377 | * Read the VME slave image base address |
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378 | */ |
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379 | temp = get_vme_base_address (); |
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380 | |
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381 | /* |
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382 | * Update the VMEbus Slave Image 0 Bound Address. |
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383 | */ |
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384 | temp = temp + (size & 0xFFFFF000); |
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385 | PCI_bus_write( &UNIVERSE->VSI0_BD, temp ); |
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386 | } |
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387 | |
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388 | #if 0 |
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389 | /* XXXXX */ |
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390 | /* |
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391 | * Returns the 16 bit location specified by vme_ptr, which must be a |
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392 | * pointer to VME D16 space |
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393 | */ |
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394 | rtems_unsigned16 get_vme( |
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395 | rtems_unsigned16 *vme_ptr |
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396 | ) |
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397 | { |
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398 | rtems_unsigned16 result; |
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399 | |
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400 | if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) |
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401 | { |
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402 | /* |
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403 | * LSI0_TO register to 0x3EFFF000 if it had not been updated already |
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404 | */ |
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405 | if (( PCI_bus_read( &UNIVERSE->LSI0_TO ) & 0xFFFFF000) != 0x3EFFF000) |
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406 | PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 ); |
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407 | |
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408 | result = (*(rtems_unsigned16 *)( |
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409 | ((rtems_unsigned32)vme_ptr - 0x3EFFF000)+ |
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410 | PPCN_60X_PCI_MEM_BASE) ); |
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411 | } |
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412 | else |
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413 | result = (*(rtems_unsigned16 *) |
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414 | ((rtems_unsigned32)vme_ptr+PPCN_60X_PCI_MEM_BASE)); |
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415 | |
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416 | return result; |
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417 | } |
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418 | |
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419 | /* |
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420 | * Stores the 16 bit word at the location specified by vme_ptr, which must |
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421 | * be a pointer to VME D16 space |
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422 | */ |
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423 | void put_vme( |
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424 | rtems_unsigned16 *vme_ptr, |
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425 | rtems_unsigned16 value |
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426 | ) |
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427 | { |
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428 | |
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429 | if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) { |
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430 | /* |
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431 | * LSI0_TO register to 0x3EFFF000 if it had not been updated already |
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432 | */ |
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433 | if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000) |
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434 | PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 ); |
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435 | |
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436 | *(rtems_unsigned16 *) (((rtems_unsigned32)vme_ptr - 0x3EFFF000) + |
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437 | PPCN_60X_PCI_MEM_BASE) = value; |
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438 | } |
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439 | else |
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440 | *(rtems_unsigned16 *)((rtems_unsigned32)vme_ptr + |
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441 | PPCN_60X_PCI_MEM_BASE) = value; |
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442 | } |
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443 | #endif |
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444 | |
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