source: rtems/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c @ 14b34738

Last change on this file since 14b34738 was 14b34738, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2003 at 5:31:07 PM

2003-09-04 Joel Sherrill <joel@…>

  • console/vga.c, universe/universe.c: Removed incorrect statement about copyright assignment.
  • Property mode set to 100644
File size: 16.2 KB
Line 
1/*
2 *  COPYRIGHT (c) 1998 by Radstone Technology
3 *
4 *
5 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
6 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
7 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
8 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
9 *
10 * You are hereby granted permission to use, copy, modify, and distribute
11 * this file, provided that this notice, plus the above copyright notice
12 * and disclaimer, appears in all copies. Radstone Technology will provide
13 * no support for this code.
14 *
15 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 * $Id$
19 */
20
21#include <rtems.h>
22#include <assert.h>
23#include <stdio.h>
24
25#include <bsp.h>
26#include <pci.h>
27
28/********************************************************************
29 ********************************************************************
30 *********                                                  *********
31 *********                  Prototypes                      *********
32 *********                                                  *********
33 ********************************************************************
34 ********************************************************************/
35
36typedef struct {
37  rtems_unsigned32 PCI_ID;                 /* Offset 0x0000 */
38  rtems_unsigned32 PCI_CSR;                /* Offset 0x0004 */
39  rtems_unsigned32 PCI_CLASS;              /* Offset 0x0008 */
40  rtems_unsigned32 PCI_MISC0;              /* Offset 0x000C */
41  rtems_unsigned32 PCI_BS;                 /* Offset 0x0010 */
42  rtems_unsigned32 Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */
43  rtems_unsigned32 PCI_MISC1;              /* Offset 0x003C */
44  rtems_unsigned32 Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */
45  rtems_unsigned32 LSI0_CTL;               /* Offset 0x0100 */
46  rtems_unsigned32 LSI0_BS;                /* Offset 0x0104 */
47  rtems_unsigned32 LSI0_BD;                /* Offset 0x0108 */
48  rtems_unsigned32 LSI0_TO;                /* Offset 0x010C */
49  rtems_unsigned32 Buf_Offset_0x0110;         /* Offset 0x0110 */
50  rtems_unsigned32 LSI1_CTL;               /* Offset 0x0114 */
51  rtems_unsigned32 LSI1_BS;                /* Offset 0x0118 */
52  rtems_unsigned32 LSI1_BD;                /* Offset 0x011C */
53  rtems_unsigned32 LSI1_TO;                /* Offset 0x0120 */
54  rtems_unsigned32 Buf_Offset_0x0124;         /* Offset 0x0124 */
55  rtems_unsigned32 LSI2_CTL;               /* Offset 0x0128 */
56  rtems_unsigned32 LSI2_BS;                /* Offset 0x012C */
57  rtems_unsigned32 LSI2_BD;                /* Offset 0x0130 */
58  rtems_unsigned32 LSI2_TO;                /* Offset 0x0134 */
59  rtems_unsigned32 Buf_Offset_0x0138;         /* Offset 0x0138 */
60  rtems_unsigned32 LSI3_CTL;               /* Offset 0x013C */
61  rtems_unsigned32 LSI3_BS;                /* Offset 0x0140 */
62  rtems_unsigned32 LSI3_BD;                /* Offset 0x0144 */
63  rtems_unsigned32 LSI3_TO;                /* Offset 0x0148 */
64  rtems_unsigned32 Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */
65  rtems_unsigned32 SCYC_CTL;               /* Offset 0x0170 */
66  rtems_unsigned32 SCYC_ADDR;              /* Offset 0x0174 */
67  rtems_unsigned32 SCYC_EN;                /* Offset 0x0178 */
68  rtems_unsigned32 SCYC_CMP;               /* Offset 0x017C */
69  rtems_unsigned32 SCYC_SWP;               /* Offset 0x0180 */
70  rtems_unsigned32 LMISC;                  /* Offset 0x0184 */
71  rtems_unsigned32 SLSI;                   /* Offset 0x0188 */
72  rtems_unsigned32 L_CMDERR;               /* Offset 0x018C */
73  rtems_unsigned32 LAERR;                  /* Offset 0x0190 */
74  rtems_unsigned32 Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */
75  rtems_unsigned32 DCTL;                   /* Offset 0x0200 */
76  rtems_unsigned32 DTBC;                   /* Offset 0x0204 */
77  rtems_unsigned32 DLA;                    /* Offset 0x0208 */
78  rtems_unsigned32 Buf_Offset_0x020C;         /* Offset 0x020C */
79  rtems_unsigned32 DVA;                    /* Offset 0x0210 */
80  rtems_unsigned32 Buf_Offset_0x0214;         /* Offset 0x0214 */
81  rtems_unsigned32 DCPP;                   /* Offset 0x0218 */
82  rtems_unsigned32 Buf_Offset_0x021C;         /* Offset 0x021C */
83  rtems_unsigned32 DGCS;                   /* Offset 0x0220 */
84  rtems_unsigned32 D_LLUE;                 /* Offset 0x0224 */
85  rtems_unsigned32 Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */
86  rtems_unsigned32 LINT_EN;                /* Offset 0x0300 */
87  rtems_unsigned32 LINT_STAT;              /* Offset 0x0304 */
88  rtems_unsigned32 LINT_MAP0;              /* Offset 0x0308 */
89  rtems_unsigned32 LINT_MAP1;              /* Offset 0x030C */
90  rtems_unsigned32 VINT_EN;                /* Offset 0x0310 */
91  rtems_unsigned32 VINT_STAT;              /* Offset 0x0314 */
92  rtems_unsigned32 VINT_MAP0;              /* Offset 0x0318 */
93  rtems_unsigned32 VINT_MAP1;              /* Offset 0x031C */
94  rtems_unsigned32 STATID;                 /* Offset 0x0320 */
95  rtems_unsigned32 V1_STATID;              /* Offset 0x0324 */
96  rtems_unsigned32 V2_STATID;              /* Offset 0x0328 */
97  rtems_unsigned32 V3_STATID;              /* Offset 0x032C */
98  rtems_unsigned32 V4_STATID;              /* Offset 0x0330 */
99  rtems_unsigned32 V5_STATID;              /* Offset 0x0334 */
100  rtems_unsigned32 V6_STATID;              /* Offset 0x0338 */
101  rtems_unsigned32 V7_STATID;              /* Offset 0x033C */
102  rtems_unsigned32 Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */
103  rtems_unsigned32 MAST_CTL;               /* Offset 0x0400 */ 
104  rtems_unsigned32 MISC_CTL;               /* Offset 0x0404 */ 
105  rtems_unsigned32 MISC_STAT;              /* Offset 0x0408 */ 
106  rtems_unsigned32 USER_AM;                /* Offset 0x040C */
107  rtems_unsigned32 Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */
108  rtems_unsigned32 VSI0_CTL;               /* Offset 0x0F00 */
109  rtems_unsigned32 VSI0_BS;                /* Offset 0x0F04 */
110  rtems_unsigned32 VSI0_BD;                /* Offset 0x0F08 */
111  rtems_unsigned32 VSI0_TO;                /* Offset 0x0F0C */
112  rtems_unsigned32 Buf_Offset_0x0f10;         /* Offset 0x0F10 */
113  rtems_unsigned32 VSI1_CTL;               /* Offset 0x0F14 */
114  rtems_unsigned32 VSI1_BS;                /* Offset 0x0F18 */
115  rtems_unsigned32 VSI1_BD;                /* Offset 0x0F1C */
116  rtems_unsigned32 VSI1_TO;                /* Offset 0x0F20 */
117  rtems_unsigned32 Buf_Offset_0x0F24;         /* Offset 0x0F24 */
118  rtems_unsigned32 VSI2_CTL;               /* Offset 0x0F28 */
119  rtems_unsigned32 VSI2_BS;                /* Offset 0x0F2C */
120  rtems_unsigned32 VSI2_BD;                /* Offset 0x0F30 */
121  rtems_unsigned32 VSI2_TO;                /* Offset 0x0F34 */
122  rtems_unsigned32 Buf_Offset_0x0F38;         /* Offset 0x0F38 */
123  rtems_unsigned32 VSI3_CTL;               /* Offset 0x0F3C */
124  rtems_unsigned32 VSI3_BS;                /* Offset 0x0F40 */
125  rtems_unsigned32 VSI3_BD;                /* Offset 0x0F44 */
126  rtems_unsigned32 VSI3_TO;                /* Offset 0x0F48 */
127  rtems_unsigned32 Buf_Offset_0x0F4C[ 0x9 ];  /* Offset 0x0F4C */
128  rtems_unsigned32 VRAI_CTL;               /* Offset 0x0F70 */
129  rtems_unsigned32 VRAI_BS;                /* Offset 0x0F74 */
130  rtems_unsigned32 Buf_Offset_0x0F78[ 0x2 ];  /* Offset 0x0F78 */
131  rtems_unsigned32 VCSR_CTL;               /* Offset 0x0F80 */
132  rtems_unsigned32 VCSR_TO;                /* Offset 0x0F84 */
133  rtems_unsigned32 V_AMERR;                /* Offset 0x0F88 */
134  rtems_unsigned32 VAERR;                  /* Offset 0x0F8C */
135  rtems_unsigned32 Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */
136  rtems_unsigned32 VCSR_CLR;               /* Offset 0x0FF4 */
137  rtems_unsigned32 VCSR_SET;               /* Offset 0x0FF8 */
138  rtems_unsigned32 VCSR_BS;                /* Offset 0x0FFC */
139} Universe_Memory;
140
141volatile Universe_Memory *UNIVERSE;
142
143/*
144 * PCI_bus_write
145 */
146void PCI_bus_write(
147  volatile rtems_unsigned32 * _addr,                  /* IN */
148  rtems_unsigned32 _data                              /* IN */
149) 
150{
151  outport_32(_addr, _data);
152}
153
154rtems_unsigned32 PCI_bus_read(
155  volatile rtems_unsigned32 *  _addr                  /* IN */
156)
157{
158  rtems_unsigned32 data;
159 
160  inport_32(_addr, data);
161  return data;
162}
163
164/********************************************************************
165 ********************************************************************
166 *********                                                  *********
167 *********                                                  *********
168 *********                                                  *********
169 ********************************************************************
170 ********************************************************************/
171
172/*
173 * Initializes the UNIVERSE chip.  This routine is called automatically
174 * by the boot code.  This routine should be called by user code only if
175 * a complete PPCn_60x VME initialization is required.
176 */
177
178void InitializeUniverse()
179{
180  rtems_unsigned32 pci_id;
181  rtems_unsigned32 universe_temp_value;
182 
183  /*
184   * Verify the UNIVERSE CHIP ID
185   */
186   (void)PCIConfigRead32(0,4,0,PCI_CONFIG_VENDOR_LOW, &pci_id);
187
188   /*
189    * compare to known ID
190    */
191   if (pci_id != 0x000010e3 ){
192     DEBUG_puts ("Invalid PPCN_60X_UNIVERSE_CHIP_ID: ");
193     rtems_fatal_error_occurred( 0x603e0bad );
194   }
195
196   (void)PCIConfigRead32(0,4,0,PCI_CONFIG_BAR_0, &universe_temp_value);
197   UNIVERSE = (Universe_Memory *)(universe_temp_value & ~PCI_ADDRESS_IO_SPACE);
198
199   /*
200    * Set the UNIVERSE PCI Configuration Space Control and Status Register to
201    * medium speed device, Target Back to Back Capable, Master Enable, Target
202    * Memory Enable and Target IO Enable
203    */
204   PCIConfigWrite32(0,4,0,PCI_CONFIG_COMMAND, PCI_ENABLE_IO_SPACE |
205                                              PCI_ENABLE_MEMORY_SPACE |
206                                              PCI_ENABLE_BUS_MASTER);
207
208   /*
209    * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
210    */
211   PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );   
212
213#if 0
214   /*
215    * Set VMEbus Slave Image 0 Base Address to 0x04000000 on VSI0_BS register.
216    */
217   PCI_bus_write( &UNIVERSE->VSI0_BS, 0x04000000 );   
218
219   /*
220    * Set VMEbus Slave Image 0 Bound Address to 0x05000000 on VSI0_BD register.
221    */
222   PCI_bus_write( &UNIVERSE->VSI0_BD, 0x05000000 );
223
224   /*
225    * VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO
226    * register. Map the VME base address 0x4000000 to local memory address 0x0
227    */
228   PCI_bus_write( &UNIVERSE->VSI0_TO, 0x7C000000 );
229
230   /*
231    * Set the VMEbus Slave Image 0 Control register with write posted,
232    * read prefetch and AM code set for program, data, supervisor and user mode
233    */
234   PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 );   
235#endif
236
237   /*
238    * Set the VMEbus Master Control register with retry forever, 256 bytes
239    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
240    * aligned burst size and PCI bus number to be zero
241    */
242   PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
243
244   /*
245    * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
246    * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
247    * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
248    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );   
249    */
250   
251   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
252   PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
253   PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
254   PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );
255
256
257#if 0
258   /*
259    * Set the PCI Slave Image 0 Control register with posted write enable,
260    * 32 bit data width, A32 VMEbus address base, AM code to be data,
261    * none-privilleged, single and BLT cycles on VME bus with PCI
262    * bus memory space.
263   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 );   
264    */
265   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );   
266
267   /*
268    * Set the PCI Slave Image 0 Base Address to be
269    * 0x0 on LSI0_BS register.
270    */
271   PCI_bus_write( &UNIVERSE->LSI0_BS, 0x00FF0000 );
272
273   /*
274    * Set the PCI Slave Image 0 Bound Address to be
275    * 0xFFFFF000 on VSI0_BD register.
276    */
277   PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 );   
278
279   /*
280    * Set the PCI Slave Image 0 Translation Offset to be
281    * 0x0 on VSI0_TO register.
282    * Note: If the actual VME address is bigger than 0x40000000, we need
283    *   to set the PCI Slave Image 0 Translation Offset = 0x40000000
284    *   register. 
285    *   i.e. if actual VME ADRR = 0x50000000, then we
286    *     need to subtract it by 0x40000000 and set
287    *      the LSI0_T0 register to be 0x40000000 and then
288    *     perform a PCI data access by adding 0xC0000000 to
289    *     0x10000000 -- which is came form the result of
290    *     (0x50000000 - 0x40000000).
291    */
292   PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 );   
293#endif
294
295   /*
296    * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
297    * BI-Mode VMEbus accesses can be made.
298    */
299
300   universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
301
302   if (universe_temp_value & 0x100000)
303     PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
304}
305
306/*
307 * Set the slave VME base address to the specified base address.
308 * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
309 *       Slave Image 0 registers.
310 */
311void set_vme_base_address (
312  rtems_unsigned32 base_address
313)
314{ 
315  volatile rtems_unsigned32 temp;
316
317  /*
318   * Calculate the current size of the Slave VME image 0
319   */
320  temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - 
321          ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
322
323  /*
324   * Set the VMEbus Slave Image 0 Base Address to be
325   * the specifed base address on VSI0_BS register.
326   */
327   PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );   
328
329  /*
330   * Update the VMEbus Slave Image 0 Bound Address.
331   */
332  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
333
334  /*
335   * Update the VMEbus Slave Image 0 Translation Offset
336   */
337  temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
338  PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
339}
340
341/*
342 * Gets the VME base address
343 */
344rtems_unsigned32 get_vme_base_address ()
345{ 
346  volatile rtems_unsigned32 temp;
347
348  temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
349  temp &= 0xFFFFF000;
350  return (temp);
351}
352
353rtems_unsigned32 get_vme_slave_size()
354{
355  volatile rtems_unsigned32 temp;
356  temp  =  PCI_bus_read( &UNIVERSE->VSI0_BD);
357  temp &= 0xFFFFF000;
358  temp  = temp - get_vme_base_address ();
359  return temp;
360}
361
362/*
363 * Set the size of the VME slave image
364 * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
365 */
366void set_vme_slave_size (rtems_unsigned32 size)
367{ 
368  volatile rtems_unsigned32 temp;
369
370  if (size<0) 
371    size = 0;
372 
373  if (size > 0x17FFFFF) 
374    size = 0x17FFFFF;
375   
376  /*
377   * Read the VME slave image base address
378   */
379  temp = get_vme_base_address ();
380
381  /*
382   * Update the VMEbus Slave Image 0 Bound Address.
383   */
384  temp = temp + (size & 0xFFFFF000);
385  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
386}
387
388#if 0
389/* XXXXX */
390/*
391 * Returns the 16 bit location specified by vme_ptr, which must be a
392 * pointer to VME D16 space
393 */
394rtems_unsigned16 get_vme(
395  rtems_unsigned16 *vme_ptr
396)
397{
398  rtems_unsigned16 result;
399
400  if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF)
401  {
402    /*
403     * LSI0_TO register to 0x3EFFF000 if it had not been updated already
404     */
405    if (( PCI_bus_read( &UNIVERSE->LSI0_TO ) & 0xFFFFF000) != 0x3EFFF000)
406         PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );
407
408    result = (*(rtems_unsigned16 *)(
409               ((rtems_unsigned32)vme_ptr - 0x3EFFF000)+
410                PPCN_60X_PCI_MEM_BASE) );
411   }
412   else
413     result = (*(rtems_unsigned16 *)
414                ((rtems_unsigned32)vme_ptr+PPCN_60X_PCI_MEM_BASE));
415
416   return result;
417}
418
419/*
420 * Stores the 16 bit word at the location specified by vme_ptr, which must
421 * be a pointer to VME D16 space
422 */
423void put_vme(
424  rtems_unsigned16 *vme_ptr,
425  rtems_unsigned16 value
426)
427{
428
429  if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) {
430    /*
431     * LSI0_TO register to 0x3EFFF000 if it had not been updated already
432     */
433     if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000)
434       PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );
435   
436    *(rtems_unsigned16 *) (((rtems_unsigned32)vme_ptr - 0x3EFFF000) +
437                            PPCN_60X_PCI_MEM_BASE) = value;
438   }
439   else
440      *(rtems_unsigned16 *)((rtems_unsigned32)vme_ptr +
441                             PPCN_60X_PCI_MEM_BASE) = value;
442}
443#endif
444
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