[0c04c377] | 1 | /* |
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| 2 | * COPYRIGHT (c) 1998 by Radstone Technology |
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| 3 | * |
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| 4 | * |
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| 5 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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| 6 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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| 7 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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| 8 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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| 9 | * |
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| 10 | * You are hereby granted permission to use, copy, modify, and distribute |
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| 11 | * this file, provided that this notice, plus the above copyright notice |
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| 12 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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| 13 | * no support for this code. |
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| 14 | * |
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| 15 | */ |
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| 16 | #include <bsp.h> |
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| 17 | #include <pci.h> |
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| 18 | |
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| 19 | /* SCE 97/4/9 |
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| 20 | * |
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| 21 | * Use PCI configuration space access mechanism 1 |
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| 22 | * |
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| 23 | * This is the preferred access mechanism and must be used when accessing |
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| 24 | * bridged PCI busses. |
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| 25 | * |
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| 26 | * The address to be written to the PCI_CONFIG_ADDRESS port is constructed |
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| 27 | * thus (the representation below is little endian): |
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| 28 | * |
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| 29 | * 31 30 24 23 16 15 11 10 8 7 2 1 0 |
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| 30 | * ---------------------------------------------------------------------- |
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| 31 | * | 1 | Resvd | Bus Number | Dev Number | Fn Number | Reg Number | 0 | 0 | |
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| 32 | * ---------------------------------------------------------------------- |
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| 33 | * |
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| 34 | * On bus 0, the first 'real' device is at Device number 11, the Eagle being |
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| 35 | * device 0. On all other busses, device numbering starts at 0. |
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| 36 | */ |
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| 37 | /* |
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| 38 | * Normal PCI device numbering on busses other than 0 is such that |
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| 39 | * that the first device (0) is attached to AD16, second (1) to AD17 etc. |
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| 40 | */ |
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| 41 | #define CONFIG_ADDRESS(Bus, Device, Function, Offset) \ |
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| 42 | (0x80000000 | (Bus<<16) | \ |
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| 43 | ((Device+(((Bus==0)&&(Device>0)) ? 10 : 0))<<11) | \ |
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| 44 | (Function<<8) | \ |
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| 45 | (Offset&~0x03)) |
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| 46 | #define BYTE_LANE_OFFSET(Offset) ((Offset)&0x3) |
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| 47 | |
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| 48 | /* |
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| 49 | * Private data |
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| 50 | */ |
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| 51 | static unsigned8 ucMaxPCIBus; |
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| 52 | |
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| 53 | /* |
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| 54 | * Public routines |
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| 55 | */ |
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| 56 | rtems_status_code PCIConfigWrite8( |
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| 57 | unsigned8 ucBusNumber, |
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| 58 | unsigned8 ucSlotNumber, |
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| 59 | unsigned8 ucFunctionNumber, |
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| 60 | unsigned8 ucOffset, |
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| 61 | unsigned8 ucValue |
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| 62 | ) |
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| 63 | { |
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| 64 | ISR_Level Irql; |
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| 65 | |
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| 66 | /* |
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| 67 | * Ensure that accesses to the addr/data ports are indivisible |
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| 68 | */ |
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| 69 | _ISR_Disable(Irql); |
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| 70 | |
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| 71 | /* |
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| 72 | * Write to the configuration space address register |
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| 73 | */ |
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| 74 | outport_32(PCI_CONFIG_ADDR, |
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| 75 | CONFIG_ADDRESS(ucBusNumber, ucSlotNumber, |
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| 76 | ucFunctionNumber, ucOffset)); |
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| 77 | /* |
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| 78 | * Write to the configuration space data register with the appropriate |
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| 79 | * offset |
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| 80 | */ |
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| 81 | outport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), ucValue); |
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| 82 | |
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| 83 | _ISR_Enable(Irql); |
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| 84 | |
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| 85 | return(RTEMS_SUCCESSFUL); |
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| 86 | } |
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| 87 | |
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| 88 | rtems_status_code PCIConfigWrite16( |
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| 89 | unsigned8 ucBusNumber, |
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| 90 | unsigned8 ucSlotNumber, |
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| 91 | unsigned8 ucFunctionNumber, |
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| 92 | unsigned8 ucOffset, |
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| 93 | unsigned16 usValue |
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| 94 | ) |
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| 95 | { |
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| 96 | ISR_Level Irql; |
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| 97 | |
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| 98 | /* |
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| 99 | * Ensure that accesses to the addr/data ports are indivisible |
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| 100 | */ |
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| 101 | _ISR_Disable(Irql); |
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| 102 | |
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| 103 | /* |
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| 104 | * Write to the configuration space address register |
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| 105 | */ |
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| 106 | outport_32(PCI_CONFIG_ADDR, |
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| 107 | CONFIG_ADDRESS(ucBusNumber, ucSlotNumber, |
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| 108 | ucFunctionNumber, ucOffset)); |
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| 109 | /* |
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| 110 | * Write to the configuration space data register with the appropriate |
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| 111 | * offset |
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| 112 | */ |
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| 113 | outport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), usValue); |
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| 114 | |
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| 115 | _ISR_Enable(Irql); |
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| 116 | |
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| 117 | return(RTEMS_SUCCESSFUL); |
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| 118 | } |
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| 119 | |
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| 120 | rtems_status_code PCIConfigWrite32( |
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| 121 | unsigned8 ucBusNumber, |
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| 122 | unsigned8 ucSlotNumber, |
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| 123 | unsigned8 ucFunctionNumber, |
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| 124 | unsigned8 ucOffset, |
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| 125 | unsigned32 ulValue |
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| 126 | ) |
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| 127 | { |
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| 128 | ISR_Level Irql; |
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| 129 | |
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| 130 | /* |
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| 131 | * Ensure that accesses to the addr/data ports are indivisible |
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| 132 | */ |
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| 133 | _ISR_Disable(Irql); |
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| 134 | |
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| 135 | /* |
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| 136 | * Write to the configuration space address register |
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| 137 | */ |
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| 138 | outport_32(PCI_CONFIG_ADDR, |
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| 139 | CONFIG_ADDRESS(ucBusNumber, ucSlotNumber, |
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| 140 | ucFunctionNumber, ucOffset)); |
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| 141 | /* |
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| 142 | * Write to the configuration space data register with the appropriate |
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| 143 | * offset |
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| 144 | */ |
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| 145 | outport_32(PCI_CONFIG_DATA, ulValue); |
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| 146 | |
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| 147 | _ISR_Enable(Irql); |
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| 148 | |
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| 149 | return(RTEMS_SUCCESSFUL); |
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| 150 | } |
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| 151 | |
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| 152 | rtems_status_code PCIConfigRead8( |
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| 153 | unsigned8 ucBusNumber, |
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| 154 | unsigned8 ucSlotNumber, |
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| 155 | unsigned8 ucFunctionNumber, |
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| 156 | unsigned8 ucOffset, |
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| 157 | unsigned8 *pucValue |
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| 158 | ) |
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| 159 | { |
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| 160 | ISR_Level Irql; |
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| 161 | |
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| 162 | /* |
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| 163 | * Ensure that accesses to the addr/data ports are indivisible |
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| 164 | */ |
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| 165 | _ISR_Disable(Irql); |
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| 166 | |
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| 167 | /* |
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| 168 | * Write to the configuration space address register |
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| 169 | */ |
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| 170 | outport_32(PCI_CONFIG_ADDR, |
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| 171 | CONFIG_ADDRESS(ucBusNumber, ucSlotNumber, |
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| 172 | ucFunctionNumber, ucOffset)); |
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| 173 | /* |
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| 174 | * Read from the configuration space data register with the appropriate |
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| 175 | * offset |
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| 176 | */ |
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| 177 | inport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pucValue); |
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| 178 | |
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| 179 | _ISR_Enable(Irql); |
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| 180 | |
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| 181 | return(RTEMS_SUCCESSFUL); |
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| 182 | } |
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| 183 | |
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| 184 | rtems_status_code PCIConfigRead16( |
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| 185 | unsigned8 ucBusNumber, |
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| 186 | unsigned8 ucSlotNumber, |
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| 187 | unsigned8 ucFunctionNumber, |
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| 188 | unsigned8 ucOffset, |
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| 189 | unsigned16 *pusValue |
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| 190 | ) |
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| 191 | { |
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| 192 | ISR_Level Irql; |
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| 193 | |
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| 194 | /* |
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| 195 | * Ensure that accesses to the addr/data ports are indivisible |
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| 196 | */ |
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| 197 | _ISR_Disable(Irql); |
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| 198 | |
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| 199 | /* |
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| 200 | * Write to the configuration space address register |
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| 201 | */ |
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| 202 | outport_32(PCI_CONFIG_ADDR, |
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| 203 | CONFIG_ADDRESS(ucBusNumber, ucSlotNumber, |
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| 204 | ucFunctionNumber, ucOffset)); |
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| 205 | /* |
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| 206 | * Read from the configuration space data register with the appropriate |
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| 207 | * offset |
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| 208 | */ |
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| 209 | inport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pusValue); |
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| 210 | |
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| 211 | _ISR_Enable(Irql); |
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| 212 | |
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| 213 | return(RTEMS_SUCCESSFUL); |
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| 214 | } |
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| 215 | |
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| 216 | rtems_status_code PCIConfigRead32( |
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| 217 | unsigned8 ucBusNumber, |
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| 218 | unsigned8 ucSlotNumber, |
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| 219 | unsigned8 ucFunctionNumber, |
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| 220 | unsigned8 ucOffset, |
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| 221 | unsigned32 *pulValue |
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| 222 | ) |
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| 223 | { |
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| 224 | ISR_Level Irql; |
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| 225 | |
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| 226 | /* |
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| 227 | * Ensure that accesses to the addr/data ports are indivisible |
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| 228 | */ |
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| 229 | _ISR_Disable(Irql); |
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| 230 | |
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| 231 | /* |
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| 232 | * Write to the configuration space address register |
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| 233 | */ |
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| 234 | outport_32(PCI_CONFIG_ADDR, |
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| 235 | CONFIG_ADDRESS(ucBusNumber, ucSlotNumber, |
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| 236 | ucFunctionNumber, ucOffset)); |
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| 237 | /* |
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| 238 | * Read from the configuration space data register with the appropriate |
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| 239 | * offset |
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| 240 | */ |
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| 241 | inport_32(PCI_CONFIG_DATA, *pulValue); |
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| 242 | |
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| 243 | _ISR_Enable(Irql); |
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| 244 | |
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| 245 | return(RTEMS_SUCCESSFUL); |
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| 246 | } |
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| 247 | |
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| 248 | /* |
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| 249 | * This routine determines the maximum bus number in the system |
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| 250 | */ |
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| 251 | void InitializePCI() |
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| 252 | { |
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| 253 | unsigned8 ucSlotNumber, ucFnNumber, ucNumFuncs; |
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| 254 | unsigned8 ucHeader; |
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| 255 | unsigned8 ucBaseClass, ucSubClass, ucMaxSubordinate; |
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| 256 | unsigned32 ulDeviceID; |
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| 257 | |
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| 258 | /* |
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| 259 | * Scan PCI bus 0 looking for PCI-PCI bridges |
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| 260 | */ |
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| 261 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) |
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| 262 | { |
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| 263 | (void)PCIConfigRead32(0, |
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| 264 | ucSlotNumber, |
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| 265 | 0, |
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| 266 | PCI_CONFIG_VENDOR_LOW, |
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| 267 | &ulDeviceID); |
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| 268 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) |
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| 269 | { |
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| 270 | /* |
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| 271 | * This slot is empty |
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| 272 | */ |
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| 273 | continue; |
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| 274 | } |
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| 275 | (void)PCIConfigRead8(0, |
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| 276 | ucSlotNumber, |
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| 277 | 0, |
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| 278 | PCI_CONFIG_HEADER_TYPE, |
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| 279 | &ucHeader); |
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| 280 | if(ucHeader&PCI_MULTI_FUNCTION) |
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| 281 | { |
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| 282 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
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| 283 | } |
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| 284 | else |
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| 285 | { |
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| 286 | ucNumFuncs=1; |
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| 287 | } |
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| 288 | for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) |
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| 289 | { |
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| 290 | (void)PCIConfigRead32(0, |
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| 291 | ucSlotNumber, |
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| 292 | ucFnNumber, |
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| 293 | PCI_CONFIG_VENDOR_LOW, |
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| 294 | &ulDeviceID); |
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| 295 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) |
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| 296 | { |
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| 297 | /* |
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| 298 | * This slot/function is empty |
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| 299 | */ |
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| 300 | continue; |
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| 301 | } |
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| 302 | |
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| 303 | /* |
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| 304 | * This slot/function has a device fitted. |
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| 305 | */ |
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| 306 | (void)PCIConfigRead8(0, |
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| 307 | ucSlotNumber, |
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| 308 | ucFnNumber, |
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| 309 | PCI_CONFIG_CLASS_CODE_U, |
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| 310 | &ucBaseClass); |
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| 311 | (void)PCIConfigRead8(0, |
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| 312 | ucSlotNumber, |
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| 313 | ucFnNumber, |
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| 314 | PCI_CONFIG_CLASS_CODE_M, |
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| 315 | &ucSubClass); |
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| 316 | if((ucBaseClass==PCI_BASE_CLASS_BRIDGE) && |
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| 317 | (ucSubClass==PCI_SUB_CLASS_BRIDGE_PCI)) |
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| 318 | { |
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| 319 | /* |
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| 320 | * We have found a PCI-PCI bridge |
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| 321 | */ |
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| 322 | (void)PCIConfigRead8(0, |
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| 323 | ucSlotNumber, |
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| 324 | ucFnNumber, |
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| 325 | PCI_BRIDGE_SUBORDINATE_BUS, |
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| 326 | &ucMaxSubordinate); |
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| 327 | if(ucMaxSubordinate>ucMaxPCIBus) |
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| 328 | { |
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| 329 | ucMaxPCIBus=ucMaxSubordinate; |
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| 330 | } |
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| 331 | } |
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| 332 | } |
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| 333 | } |
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| 334 | } |
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| 335 | |
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| 336 | /* |
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| 337 | * Return the number of PCI busses in the system |
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| 338 | */ |
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| 339 | unsigned8 BusCountPCI() |
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| 340 | { |
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| 341 | return(ucMaxPCIBus+1); |
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| 342 | } |
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