1 | /* |
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2 | * This file contains the NvRAM driver for the PPCn_60x |
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3 | * |
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4 | * COPYRIGHT (c) 1998 by Radstone Technology |
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5 | * |
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6 | * |
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7 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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8 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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9 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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10 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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11 | * |
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12 | * You are hereby granted permission to use, copy, modify, and distribute |
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13 | * this file, provided that this notice, plus the above copyright notice |
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14 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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15 | * no support for this code. |
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16 | * |
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17 | */ |
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18 | |
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19 | #include <bsp.h> |
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20 | #include "ds1385.h" |
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21 | #include "mk48t18.h" |
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22 | #include "stk11c68.h" |
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23 | |
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24 | /* |
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25 | * Private types |
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26 | */ |
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27 | typedef |
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28 | void |
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29 | (*PNVRAMWRITE) |
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30 | ( |
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31 | unsigned32 ulOffset, |
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32 | unsigned8 ucByte |
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33 | ); |
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34 | |
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35 | typedef |
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36 | unsigned8 |
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37 | (*PNVRAMREAD) |
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38 | ( |
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39 | unsigned32 ulOffset |
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40 | ); |
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41 | |
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42 | typedef |
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43 | void |
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44 | (*PNVRAMCOMMIT) |
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45 | ( |
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46 | ); |
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47 | |
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48 | typedef struct _NVRAM_ENTRY_TABLE |
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49 | { |
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50 | PNVRAMWRITE nvramWrite; |
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51 | PNVRAMREAD nvramRead; |
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52 | PNVRAMCOMMIT nvramCommit; |
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53 | unsigned32 nvramSize; |
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54 | } NVRAM_ENTRY_TABLE, *PNVRAM_ENTRY_TABLE; |
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55 | |
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56 | /* |
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57 | * Private routines |
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58 | */ |
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59 | |
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60 | /* |
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61 | * This routine provides a stub for NvRAM devices which |
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62 | * do not require a commit operation |
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63 | */ |
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64 | static void nvramCommitStub(); |
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65 | |
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66 | /* |
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67 | * DS1385 specific routines |
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68 | */ |
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69 | static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucByte); |
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70 | static unsigned8 nvramDsRead(unsigned32 ulOffset); |
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71 | |
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72 | /* |
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73 | * MK48T18 specific routines |
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74 | */ |
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75 | static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucByte); |
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76 | static unsigned8 nvramMkRead(unsigned32 ulOffset); |
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77 | |
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78 | /* |
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79 | * STK11C68 specific routines |
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80 | */ |
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81 | static void nvramStk11C68Commit(); |
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82 | /* |
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83 | * STK11C88 specific routines |
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84 | */ |
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85 | static void nvramStk11C88Commit(); |
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86 | |
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87 | /* |
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88 | * NvRAM hook tables |
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89 | */ |
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90 | NVRAM_ENTRY_TABLE nvramDsTable = |
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91 | { |
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92 | nvramDsWrite, |
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93 | nvramDsRead, |
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94 | nvramCommitStub, |
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95 | DS1385_NVSIZE |
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96 | }; |
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97 | |
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98 | NVRAM_ENTRY_TABLE nvramMkTable = |
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99 | { |
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100 | nvramMkWrite, |
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101 | nvramMkRead, |
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102 | nvramCommitStub, |
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103 | MK48T18_NVSIZE |
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104 | }; |
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105 | |
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106 | /* |
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107 | * As the STK devicxe is at the same address as the MK device, |
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108 | * the MK read/write routines may be used |
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109 | */ |
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110 | NVRAM_ENTRY_TABLE nvramStkTable = |
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111 | { |
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112 | nvramMkWrite, |
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113 | nvramMkRead, |
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114 | nvramStk11C68Commit, |
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115 | STK11C68_NVSIZE |
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116 | }; |
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117 | |
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118 | NVRAM_ENTRY_TABLE nvramStk88Table = |
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119 | { |
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120 | nvramMkWrite, |
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121 | nvramMkRead, |
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122 | nvramStk11C88Commit, |
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123 | STK11C88_NVSIZE |
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124 | }; |
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125 | |
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126 | /* |
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127 | * Private variables |
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128 | */ |
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129 | static PNVRAM_ENTRY_TABLE pNvRAMFunc; |
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130 | static boolean bNvRAMChanged=FALSE; |
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131 | static unsigned32 ulPRePOSAreaLength; |
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132 | static unsigned32 ulPRePOSAreaOffset; |
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133 | |
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134 | /* |
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135 | * Mutual-exclusion semaphore |
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136 | */ |
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137 | static rtems_id semNvRAM; |
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138 | |
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139 | /* |
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140 | * These routines support the ds1385 |
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141 | */ |
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142 | static unsigned8 nvramDsRead(unsigned32 ulOffset) |
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143 | { |
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144 | unsigned8 ucTemp; |
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145 | |
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146 | ucTemp = ulOffset & 0xff; |
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147 | outport_byte(DS1385_PORT_BASE, ucTemp); |
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148 | |
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149 | ucTemp = (ulOffset >> 8) & 0xf; |
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150 | outport_byte((DS1385_PORT_BASE + 1) , ucTemp); |
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151 | |
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152 | inport_byte(DS1385_PORT_BASE+3, ucTemp); |
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153 | return(ucTemp); |
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154 | } |
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155 | |
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156 | static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucData) |
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157 | { |
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158 | unsigned8 ucTemp; |
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159 | |
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160 | ucTemp = (unsigned8)(ulOffset & 0xff); |
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161 | outport_byte(DS1385_PORT_BASE, (unsigned8) ucTemp); |
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162 | |
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163 | ucTemp = (unsigned8)((ulOffset >> 8) & 0xf); |
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164 | outport_byte((DS1385_PORT_BASE + 1) , (unsigned8)ucTemp); |
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165 | |
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166 | outport_byte((DS1385_PORT_BASE+3), ucData); |
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167 | } |
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168 | |
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169 | /* |
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170 | * These routines support the MK48T18 and STK11C68 |
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171 | */ |
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172 | static unsigned8 nvramMkRead(unsigned32 ulOffset) |
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173 | { |
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174 | unsigned8 *pNvRAM = (unsigned8 *)MK48T18_BASE; |
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175 | |
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176 | return(pNvRAM[ulOffset]); |
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177 | } |
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178 | |
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179 | static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucData) |
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180 | { |
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181 | unsigned8 *pNvRAM = (unsigned8 *)MK48T18_BASE; |
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182 | |
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183 | pNvRAM[ulOffset]=ucData; |
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184 | } |
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185 | |
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186 | /* |
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187 | * This routine provides a stub for NvRAM devices which |
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188 | * do not require a commit operation |
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189 | */ |
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190 | static void nvramCommitStub() |
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191 | { |
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192 | } |
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193 | |
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194 | /* |
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195 | * This routine triggers a transfer from the NvRAM to the |
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196 | * EE array in the STK11C68 device |
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197 | */ |
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198 | static void nvramStk11C68Commit() |
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199 | { |
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200 | #if 0 |
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201 | rtems_interval ticks_per_second; |
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202 | rtems_status_code status; |
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203 | #endif |
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204 | |
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205 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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206 | /* |
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207 | * Issue Store command |
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208 | */ |
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209 | EIEIO; |
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210 | (void)pNvRAMFunc->nvramRead(0x0000); |
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211 | EIEIO; |
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212 | (void)pNvRAMFunc->nvramRead(0x1555); |
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213 | EIEIO; |
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214 | (void)pNvRAMFunc->nvramRead(0x0aaa); |
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215 | EIEIO; |
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216 | (void)pNvRAMFunc->nvramRead(0x1fff); |
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217 | EIEIO; |
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218 | (void)pNvRAMFunc->nvramRead(0x10f0); |
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219 | EIEIO; |
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220 | (void)pNvRAMFunc->nvramRead(0x0f0f); |
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221 | EIEIO; |
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222 | /* |
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223 | * Delay for 10mS to allow store to |
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224 | * complete |
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225 | */ |
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226 | #if 0 |
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227 | status = rtems_clock_get( |
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228 | RTEMS_CLOCK_GET_TICKS_PER_SECOND, |
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229 | &ticks_per_second |
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230 | ); |
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231 | |
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232 | status = rtems_task_wake_after(ticks_per_second/100); |
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233 | #endif |
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234 | bNvRAMChanged=FALSE; |
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235 | |
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236 | rtems_semaphore_release(semNvRAM); |
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237 | } |
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238 | |
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239 | /* |
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240 | * This routine triggers a transfer from the NvRAM to the |
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241 | * EE array in the STK11C88 device |
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242 | */ |
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243 | static void nvramStk11C88Commit() |
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244 | { |
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245 | #if 0 |
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246 | rtems_interval ticks_per_second; |
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247 | rtems_status_code status; |
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248 | #endif |
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249 | |
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250 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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251 | /* |
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252 | * Issue Store command |
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253 | */ |
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254 | EIEIO; |
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255 | (void)pNvRAMFunc->nvramRead(0x0e38); |
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256 | EIEIO; |
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257 | (void)pNvRAMFunc->nvramRead(0x31c7); |
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258 | EIEIO; |
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259 | (void)pNvRAMFunc->nvramRead(0x03e0); |
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260 | EIEIO; |
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261 | (void)pNvRAMFunc->nvramRead(0x3c1f); |
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262 | EIEIO; |
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263 | (void)pNvRAMFunc->nvramRead(0x303f); |
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264 | EIEIO; |
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265 | (void)pNvRAMFunc->nvramRead(0x0fc0); |
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266 | EIEIO; |
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267 | /* |
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268 | * Delay for 10mS to allow store to |
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269 | * complete |
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270 | */ |
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271 | #if 0 |
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272 | status = rtems_clock_get( |
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273 | RTEMS_CLOCK_GET_TICKS_PER_SECOND, |
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274 | &ticks_per_second |
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275 | ); |
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276 | |
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277 | status = rtems_task_wake_after(ticks_per_second/100); |
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278 | #endif |
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279 | bNvRAMChanged=FALSE; |
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280 | |
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281 | rtems_semaphore_release(semNvRAM); |
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282 | } |
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283 | |
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284 | /* |
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285 | * These are the publically accessable routines |
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286 | */ |
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287 | /* |
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288 | * This routine returns the size of the NvRAM |
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289 | */ |
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290 | unsigned32 SizeNvRAM() |
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291 | { |
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292 | return(ulPRePOSAreaLength); |
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293 | } |
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294 | |
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295 | /* |
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296 | * This routine commits changes to the NvRAM |
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297 | */ |
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298 | void CommitNvRAM() |
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299 | { |
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300 | if(bNvRAMChanged) |
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301 | { |
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302 | (pNvRAMFunc->nvramCommit)(); |
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303 | } |
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304 | } |
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305 | |
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306 | /* |
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307 | * This routine reads a byte from the NvRAM |
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308 | */ |
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309 | rtems_status_code ReadNvRAM8(unsigned32 ulOffset, unsigned8 *pucData) |
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310 | { |
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311 | if(ulOffset>ulPRePOSAreaLength) |
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312 | { |
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313 | return RTEMS_INVALID_ADDRESS; |
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314 | } |
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315 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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316 | *pucData=pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset); |
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317 | rtems_semaphore_release(semNvRAM); |
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318 | return(RTEMS_SUCCESSFUL); |
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319 | } |
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320 | |
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321 | /* |
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322 | * This routine writes a byte to the NvRAM |
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323 | */ |
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324 | rtems_status_code WriteNvRAM8(unsigned32 ulOffset, unsigned8 ucValue) |
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325 | { |
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326 | if(ulOffset>ulPRePOSAreaLength) |
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327 | { |
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328 | return RTEMS_INVALID_ADDRESS; |
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329 | } |
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330 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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331 | pNvRAMFunc->nvramWrite(ulPRePOSAreaOffset+ulOffset, ucValue); |
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332 | bNvRAMChanged=TRUE; |
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333 | rtems_semaphore_release(semNvRAM); |
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334 | return(RTEMS_SUCCESSFUL); |
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335 | } |
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336 | |
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337 | /* |
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338 | * This routine reads a block of bytes from the NvRAM |
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339 | */ |
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340 | rtems_status_code ReadNvRAMBlock( |
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341 | unsigned32 ulOffset, unsigned8 *pucData, unsigned32 length) |
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342 | { |
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343 | unsigned32 i; |
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344 | |
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345 | if((ulOffset + length) > ulPRePOSAreaLength) |
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346 | { |
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347 | return RTEMS_INVALID_ADDRESS; |
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348 | } |
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349 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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350 | for ( i=0 ; i<length ; i++ ) |
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351 | pucData[i] = |
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352 | pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset+i); |
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353 | rtems_semaphore_release(semNvRAM); |
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354 | return(RTEMS_SUCCESSFUL); |
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355 | } |
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356 | |
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357 | /* |
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358 | * This routine writes a block of bytes to the NvRAM |
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359 | */ |
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360 | rtems_status_code WriteNvRAMBlock( |
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361 | unsigned32 ulOffset, unsigned8 *ucValue, unsigned32 length) |
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362 | { |
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363 | unsigned32 i; |
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364 | |
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365 | if((ulOffset + length) > ulPRePOSAreaLength) |
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366 | { |
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367 | return RTEMS_INVALID_ADDRESS; |
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368 | } |
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369 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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370 | |
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371 | for ( i=0 ; i<length ; i++ ) |
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372 | pNvRAMFunc->nvramWrite( |
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373 | ulPRePOSAreaOffset+ulOffset+i, ucValue[i]); |
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374 | bNvRAMChanged=TRUE; |
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375 | rtems_semaphore_release(semNvRAM); |
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376 | return(RTEMS_SUCCESSFUL); |
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377 | } |
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378 | |
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379 | /* |
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380 | * The NVRAM holds data in Big-Endian format |
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381 | */ |
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382 | rtems_status_code ReadNvRAM16 (unsigned32 ulOffset, unsigned16 *pusData) |
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383 | { |
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384 | unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset; |
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385 | |
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386 | if(ulOffset>ulPRePOSAreaLength) |
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387 | { |
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388 | return RTEMS_INVALID_ADDRESS; |
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389 | } |
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390 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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391 | *pusData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 8) + |
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392 | (pNvRAMFunc->nvramRead(ulTrueOffset + 1)); |
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393 | rtems_semaphore_release(semNvRAM); |
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394 | return(RTEMS_SUCCESSFUL); |
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395 | } |
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396 | |
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397 | rtems_status_code WriteNvRAM16 (unsigned32 ulOffset, unsigned16 usValue) |
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398 | { |
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399 | unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset; |
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400 | |
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401 | if(ulOffset>ulPRePOSAreaLength) |
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402 | { |
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403 | return RTEMS_INVALID_ADDRESS; |
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404 | } |
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405 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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406 | pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (usValue >> 8)); |
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407 | pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) usValue); |
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408 | bNvRAMChanged=TRUE; |
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409 | rtems_semaphore_release(semNvRAM); |
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410 | return(RTEMS_SUCCESSFUL); |
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411 | } |
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412 | |
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413 | rtems_status_code ReadNvRAM32 (unsigned32 ulOffset, unsigned32 *pulData) |
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414 | { |
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415 | unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset; |
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416 | |
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417 | if(ulOffset>ulPRePOSAreaLength) |
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418 | { |
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419 | return RTEMS_INVALID_ADDRESS; |
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420 | } |
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421 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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422 | *pulData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 24) + |
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423 | (pNvRAMFunc->nvramRead(ulTrueOffset + 1) << 16) + |
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424 | (pNvRAMFunc->nvramRead(ulTrueOffset + 2) << 8) + |
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425 | (pNvRAMFunc->nvramRead(ulTrueOffset + 3)); |
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426 | rtems_semaphore_release(semNvRAM); |
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427 | return(RTEMS_SUCCESSFUL); |
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428 | } |
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429 | |
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430 | rtems_status_code WriteNvRAM32 (unsigned32 ulOffset, unsigned32 ulValue) |
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431 | { |
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432 | unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset; |
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433 | |
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434 | if(ulOffset>ulPRePOSAreaLength) |
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435 | { |
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436 | return RTEMS_INVALID_ADDRESS; |
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437 | } |
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438 | rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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439 | pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (ulValue >> 24)); |
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440 | pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) (ulValue >> 16)); |
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441 | pNvRAMFunc->nvramWrite(ulTrueOffset + 2, (unsigned8) (ulValue >> 8)); |
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442 | pNvRAMFunc->nvramWrite(ulTrueOffset + 3, (unsigned8) ulValue); |
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443 | bNvRAMChanged=TRUE; |
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444 | rtems_semaphore_release(semNvRAM); |
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445 | return(RTEMS_SUCCESSFUL); |
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446 | } |
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447 | |
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448 | void |
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449 | InitializeNvRAM(void) |
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450 | { |
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451 | PHEADER pNvHeader = (PHEADER)0; |
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452 | rtems_status_code sc; |
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453 | unsigned32 ulLength, ulOffset; |
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454 | |
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455 | if(ucSystemType==SYS_TYPE_PPC1) |
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456 | { |
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457 | if(ucBoardRevMaj<5) |
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458 | { |
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459 | pNvRAMFunc=&nvramDsTable; |
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460 | } |
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461 | else |
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462 | { |
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463 | pNvRAMFunc=&nvramMkTable; |
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464 | } |
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465 | } |
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466 | else if(ucSystemType==SYS_TYPE_PPC1a) |
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467 | { |
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468 | pNvRAMFunc=&nvramMkTable; |
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469 | } |
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470 | else if(ucSystemType==SYS_TYPE_PPC4) |
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471 | { |
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472 | pNvRAMFunc=&nvramStk88Table; |
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473 | } |
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474 | else |
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475 | { |
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476 | pNvRAMFunc=&nvramStkTable; |
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477 | } |
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478 | |
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479 | /* |
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480 | * Set up mutex semaphore |
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481 | */ |
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482 | sc = rtems_semaphore_create ( |
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483 | rtems_build_name ('N', 'V', 'R', 's'), |
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484 | 1, |
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485 | RTEMS_BINARY_SEMAPHORE | |
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486 | RTEMS_INHERIT_PRIORITY | |
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487 | RTEMS_PRIORITY, |
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488 | RTEMS_NO_PRIORITY, |
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489 | &semNvRAM); |
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490 | if (sc != RTEMS_SUCCESSFUL) |
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491 | { |
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492 | rtems_fatal_error_occurred (sc); |
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493 | } |
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494 | |
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495 | /* |
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496 | * Initially access the whole of NvRAM until we determine where the |
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497 | * OS Area is located. |
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498 | */ |
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499 | ulPRePOSAreaLength=0xffffffff; |
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500 | ulPRePOSAreaOffset=0; |
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501 | |
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502 | /* |
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503 | * Access the header at the start of NvRAM |
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504 | */ |
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505 | ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaLength), &ulLength); |
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506 | ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaAddress), &ulOffset); |
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507 | |
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508 | /* |
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509 | * Now set limits for future accesses |
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510 | */ |
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511 | ulPRePOSAreaLength=ulLength; |
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512 | ulPRePOSAreaOffset=ulOffset; |
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513 | } |
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514 | |
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515 | |
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