source: rtems/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h @ eba2e4f

4.104.114.84.95
Last change on this file since eba2e4f was 0c04c377, checked in by Joel Sherrill <joel.sherrill@…>, on 02/18/99 at 16:48:14

./clock/Makefile.in,v
./clock/clock.c,v
./console/Makefile.in,v
./console/config.c,v
./console/console.c,v
./console/console.h,v
./console/debugio.c,v
./console/i8042.c,v
./console/i8042_p.h,v
./console/i8042vga.c,v
./console/i8042vga.h,v
./console/ns16550.c,v
./console/ns16550.h,v
./console/ns16550_p.h,v
./console/ns16550cfg.c,v
./console/ns16550cfg.h,v
./console/vga.c,v
./console/vga_p.h,v
./console/z85c30.c,v
./console/z85c30.h,v
./console/z85c30_p.h,v
./console/z85c30cfg.c,v
./console/z85c30cfg.h,v
./include/Makefile.in,v
./include/bsp.h,v
./include/chain.h,v
./include/coverhd.h,v
./include/extisrdrv.h,v
./include/nvram.h,v
./include/pci.h,v
./include/tod.h,v
./network/Makefile.in,v
./network/amd79c970.c,v
./network/amd79c970.h,v
./nvram/Makefile.in,v
./nvram/ds1385.h,v
./nvram/mk48t18.h,v
./nvram/nvram.c,v
./nvram/prepnvr.h,v
./nvram/stk11c68.h,v
./pci/Makefile.in,v
./pci/pci.c,v
./start/Makefile.in,v
./start/start.s,v
./startup/Makefile.in,v
./startup/bspclean.c,v
./startup/bspstart.c,v
./startup/bsptrap.s,v
./startup/device-tree,v
./startup/genpvec.c,v
./startup/linkcmds,v
./startup/rtems-ctor.cc,v
./startup/sbrk.c,v
./startup/setvec.c,v
./startup/spurious.c,v
./startup/swap.c,v
./timer/Makefile.in,v
./timer/timer.c,v
./tod/Makefile.in,v
./tod/cmos.h,v
./tod/tod.c,v
./universe/Makefile.in,v
./universe/universe.c,v
./vectors/Makefile.in,v
./vectors/README,v
./vectors/align_h.s,v
./vectors/vectors.s,v
./wrapup/Makefile.in,v
./Makefile.in,v
./README,v
./STATUS,v
./bsp_specs,v
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1/*
2 *  COPYRIGHT (c) 1998 by Radstone Technology
3 *
4 *
5 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
6 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
7 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
8 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
9 *
10 * You are hereby granted permission to use, copy, modify, and distribute
11 * this file, provided that this notice, plus the above copyright notice
12 * and disclaimer, appears in all copies. Radstone Technology will provide
13 * no support for this code.
14 *
15 */
16
17/*
18 * Definitions for the mk48t18 RTC/NvRAM
19 */
20
21#ifndef _MK48T18_H
22#define _MK48T18_H
23
24#include "prepnvr.h"
25
26/*
27 * This structure maps to the top of the NvRAM. It is based on the standard
28 * CMOS.h file for the ds1385. Feature and system dependant areas are preserved
29 * for potential compatibility issues.
30 *
31 * The CRC's are computed with x**16+x**12+x**5 + 1 polynomial
32 * The clock is kept in 24 hour BCD mode and should be set to UT(GMT)
33 */
34 
35typedef struct _MK48T18_CMOS_MAP {
36    unsigned8 SystemDependentArea2[8];
37    unsigned8 FeatureByte0[1];
38    unsigned8 FeatureByte1[1];
39    unsigned8 Century;       /* century byte in BCD */
40    unsigned8 FeatureByte3[1];
41    unsigned8 FeatureByte4[1];
42    unsigned8 FeatureByte5[1];
43    unsigned8 FeatureByte6[1];
44    unsigned8 FeatureByte7[1];
45    unsigned8 BootPW[14];
46    rtems_unsigned16 BootCrc; /* CRC on BootPW */
47    unsigned8 ConfigPW[14];
48    rtems_unsigned16 ConfigCrc; /* CRC on ConfigPW */
49    unsigned8 SystemDependentArea1[8];
50    /*
51     * The following are the RTC registers
52     */
53    volatile unsigned8 Control;
54    volatile unsigned8 Second:7;        /* 0-59 */
55    volatile unsigned8 Stop:1;
56    volatile unsigned8 Minute;  /* 0-59 */
57    volatile unsigned8 Hour;    /* 0-23 */
58    volatile unsigned8 Day:3;   /* 1-7 */
59    volatile unsigned8 Resvd1:3;        /* 0 */
60    volatile unsigned8 FT:1;    /* Frequency test bit - must be 0 */
61    volatile unsigned8 Resvd2:1;        /* 0 */
62    volatile unsigned8 Date;    /* 1-31 */
63    volatile unsigned8 Month;   /* 1-12 */
64    volatile unsigned8 Year;    /* 0-99 */
65} MK48T18_CMOS_MAP, *PMK48T18_CMOS_MAP;
66
67/*
68 * Control register definitions
69 */
70#define MK48T18_CTRL_WRITE      0x80
71#define MK48T18_CTRL_READ       0x40
72#define MK48T18_CTRL_SIGN       0x20
73
74#define MK48T18_NVSIZE 8192-sizeof(MK48T18_CMOS_MAP)
75#define MK48T18_GESIZE (MK48T18_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))
76#define MK48T18_BASE (PMK48T18_NVRAM_MAP)((unsigned8 *)PCI_MEM_BASE+0x00800000)
77
78/* Here is the whole map of the MK48T18 NVRAM */
79typedef struct _MK48T18_NVRAM_MAP {
80    HEADER      Header;
81    unsigned8   GEArea[MK48T18_GESIZE];
82    unsigned8   OSArea[OSAREASIZE];
83    unsigned8   ConfigArea[CONFSIZE];
84    MK48T18_CMOS_MAP    CMOS;
85} MK48T18_NVRAM_MAP, *PMK48T18_NVRAM_MAP;
86
87#endif /* _MK48T18_H */
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