1 | /* |
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2 | * COPYRIGHT (c) 1998 by Radstone Technology |
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3 | * |
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4 | * |
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5 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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6 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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7 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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8 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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9 | * |
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10 | * You are hereby granted permission to use, copy, modify, and distribute |
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11 | * this file, provided that this notice, plus the above copyright notice |
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12 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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13 | * no support for this code. |
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14 | * |
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15 | */ |
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16 | /* |
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17 | * RTEMS/KA9Q driver for PC-NET |
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18 | */ |
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19 | #include <bsp.h> |
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20 | #include <rtems/error.h> |
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21 | #include <ka9q/rtems_ka9q.h> |
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22 | #include <ka9q/global.h> |
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23 | #include <ka9q/enet.h> |
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24 | #include <ka9q/iface.h> |
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25 | #include <ka9q/netuser.h> |
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26 | #include <ka9q/trace.h> |
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27 | #include <ka9q/commands.h> |
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28 | |
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29 | #include <pci.h> |
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30 | #include "amd79c970.h" |
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31 | |
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32 | /* |
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33 | * Number of PC-NETs supported by this driver |
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34 | */ |
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35 | #define NPCNETDRIVER 1 |
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36 | |
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37 | /* |
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38 | * Default number of buffer descriptors set aside for this driver. |
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39 | * The number of transmit buffer descriptors has to be quite large |
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40 | * since a single frame often uses four or more buffer descriptors. |
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41 | * |
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42 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). |
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43 | */ |
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44 | #define LANCE_LOG2_TX_BUFFERS 4 |
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45 | #define LANCE_LOG2_RX_BUFFERS 4 |
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46 | #define TX_RING_SIZE (1 << (LANCE_LOG2_TX_BUFFERS)) |
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47 | #define TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
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48 | #define TX_RING_LEN_BITS ((LANCE_LOG2_TX_BUFFERS) << 4) |
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49 | #define RX_RING_SIZE (1 << (LANCE_LOG2_RX_BUFFERS)) |
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50 | #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) |
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51 | #define RX_RING_LEN_BITS ((LANCE_LOG2_RX_BUFFERS) << 4) |
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52 | |
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53 | /* |
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54 | * RTEMS event used by interrupt handler to signal daemons. |
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55 | * This must *not* be the same event used by the KA9Q task synchronization. |
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56 | */ |
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57 | #define INTERRUPT_EVENT RTEMS_EVENT_1 |
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58 | |
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59 | /* |
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60 | * Receive buffer size -- Allow for a full ethernet packet plus a pointer |
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61 | */ |
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62 | #define ETHPKT_SIZE 1520 |
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63 | #define RBUF_SIZE (ETHPKT_SIZE + sizeof (struct iface *)) |
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64 | |
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65 | /* |
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66 | * LANCE Register Access Macros |
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67 | */ |
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68 | #define PCNET_IO_RD32(dp, reg, value) \ |
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69 | inport_32(&dp->pPCNet->u.dwio.##reg, value) |
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70 | #define PCNET_IO_WR32(dp, reg, value) \ |
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71 | outport_32(&dp->pPCNet->u.dwio.##reg, value) |
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72 | |
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73 | /* |
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74 | * LANCE Register Access Macros |
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75 | */ |
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76 | #define RD_CSR32(dp, index, value) \ |
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77 | PCNET_IO_WR32(dp, rap, index); \ |
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78 | PCNET_IO_RD32(dp, rdp, value) |
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79 | |
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80 | #define WR_CSR32(dp, index, value) \ |
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81 | PCNET_IO_WR32(dp, rap, index); \ |
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82 | PCNET_IO_WR32(dp, rdp, value) |
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83 | |
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84 | #define RD_BCR32(dp, index, value) \ |
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85 | PCNET_IO_WR32(dp, rap, index); \ |
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86 | PCNET_IO_RD32(dp, bdp, value) |
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87 | |
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88 | #define WR_BCR32(dp, index, value) \ |
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89 | PCNET_IO_WR32(dp, rap, index); \ |
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90 | PCNET_IO_WR32(dp, bdp, value) |
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91 | |
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92 | /* |
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93 | * Hardware-specific storage |
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94 | * |
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95 | * Note that the enetInitBlk field must be aligned to a 16 byte |
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96 | * boundary |
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97 | */ |
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98 | typedef struct amd79c970Context { |
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99 | rmde_t rxBdBase[RX_RING_SIZE]; |
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100 | tmde_t txBdBase[TX_RING_SIZE]; |
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101 | initblk_t initBlk; |
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102 | pc_net_t *pPCNet; |
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103 | uint32_t ulIntVector; |
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104 | struct mbuf **rxMbuf; |
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105 | struct mbuf **txMbuf; |
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106 | int rxBdCount; |
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107 | int txBdCount; |
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108 | int txBdHead; |
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109 | int txBdTail; |
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110 | int txBdActiveCount; |
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111 | struct iface *iface; |
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112 | rtems_id txWaitTid; |
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113 | |
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114 | /* |
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115 | * Statistics |
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116 | */ |
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117 | unsigned long rxInterrupts; |
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118 | unsigned long rxNotFirst; |
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119 | unsigned long rxNotLast; |
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120 | unsigned long rxGiant; |
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121 | unsigned long rxNonOctet; |
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122 | unsigned long rxRunt; |
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123 | unsigned long rxBadCRC; |
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124 | unsigned long rxOverrun; |
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125 | unsigned long rxCollision; |
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126 | unsigned long rxDiscarded; |
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127 | |
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128 | unsigned long txInterrupts; |
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129 | unsigned long txDeferred; |
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130 | unsigned long txHeartbeat; |
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131 | unsigned long txLateCollision; |
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132 | unsigned long txRetryLimit; |
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133 | unsigned long txUnderrun; |
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134 | unsigned long txLostCarrier; |
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135 | unsigned long txRawWait; |
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136 | } amd79c970Context_t; |
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137 | static amd79c970Context_t *pAmd79c970Context[NPCNETDRIVER]; |
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138 | |
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139 | /* |
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140 | * PC-NET interrupt handler |
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141 | */ |
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142 | static rtems_isr |
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143 | amd79c970_isr (rtems_vector_number v) |
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144 | { |
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145 | uint32_t ulCSR0, ulCSR4, ulCSR5; |
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146 | amd79c970Context_t *dp; |
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147 | int i; |
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148 | |
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149 | for(i=0; i<NPCNETDRIVER; i++) |
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150 | { |
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151 | dp=pAmd79c970Context[i]; |
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152 | if(dp->ulIntVector==v) |
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153 | { |
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154 | RD_CSR32(dp, CSR0, ulCSR0); |
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155 | if(ulCSR0 & CSR0_RINT) |
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156 | { |
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157 | /* |
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158 | * We have recieve data |
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159 | */ |
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160 | dp->rxInterrupts++; |
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161 | rtems_event_send( |
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162 | dp->iface->rxproc, |
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163 | INTERRUPT_EVENT); |
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164 | } |
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165 | |
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166 | if(ulCSR0 & CSR0_TINT) |
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167 | { |
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168 | /* |
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169 | * Data tranmitted or error |
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170 | */ |
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171 | dp->txInterrupts++; |
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172 | if(dp->txWaitTid) |
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173 | { |
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174 | rtems_event_send( |
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175 | dp->txWaitTid, |
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176 | INTERRUPT_EVENT); |
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177 | } |
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178 | } |
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179 | |
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180 | if((ulCSR0 & CSR0_INTR) && |
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181 | !(ulCSR0 & (CSR0_RINT | CSR0_TINT))) |
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182 | { |
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183 | /* |
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184 | * Many possible sources |
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185 | */ |
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186 | RD_CSR32(dp, CSR4, ulCSR4); |
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187 | RD_CSR32(dp, CSR5, ulCSR5); |
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188 | DEBUG_puts("CSR0="); |
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189 | DEBUG_puth(ulCSR0); |
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190 | DEBUG_puts(", CSR4="); |
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191 | DEBUG_puth(ulCSR4); |
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192 | DEBUG_puts(", CSR5="); |
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193 | DEBUG_puth(ulCSR5); |
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194 | DEBUG_puts("\n\r"); |
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195 | /* |
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196 | * Clear it |
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197 | */ |
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198 | WR_CSR32(dp, CSR4, ulCSR4); |
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199 | WR_CSR32(dp, CSR5, ulCSR5); |
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200 | } |
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201 | |
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202 | /* |
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203 | * Clear interrupts |
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204 | */ |
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205 | ulCSR0&=CSR0_BABL | CSR0_CERR | CSR0_MISS | |
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206 | CSR0_MERR | CSR0_RINT | CSR0_TINT | CSR0_IENA; |
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207 | WR_CSR32(dp, CSR0, ulCSR0); |
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208 | |
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209 | RD_CSR32(dp, CSR0, ulCSR0); |
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210 | } |
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211 | } |
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212 | } |
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213 | |
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214 | /* |
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215 | * Initialize the ethernet hardware |
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216 | */ |
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217 | static boolean |
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218 | amd79c970_initialize_hardware (int instance, int broadcastFlag) |
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219 | { |
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220 | amd79c970Context_t *dp; |
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221 | struct mbuf *bp; |
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222 | int i; |
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223 | uint8_t ucPCIBusCount; |
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224 | uint8_t ucBusNumber; |
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225 | uint8_t ucSlotNumber; |
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226 | uint32_t ulDeviceID; |
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227 | uint32_t ulBAR0; |
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228 | uint8_t ucIntVector; |
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229 | uint32_t ulInitClkPCIAddr; |
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230 | uint32_t ulAPROM; |
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231 | uint32_t ulCSR0; |
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232 | |
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233 | ucPCIBusCount=BusCountPCI(); |
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234 | |
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235 | /* |
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236 | * Scan the available busses for instance of hardware |
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237 | */ |
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238 | i=0; |
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239 | |
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240 | dp=pAmd79c970Context[instance]; |
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241 | dp->pPCNet=(pc_net_t *)NULL; |
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242 | |
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243 | for(ucBusNumber=0; |
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244 | (ucBusNumber<ucPCIBusCount) && (dp->pPCNet==(pc_net_t *)NULL); |
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245 | ucBusNumber++) |
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246 | { |
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247 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) |
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248 | { |
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249 | PCIConfigRead32(ucBusNumber, |
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250 | ucSlotNumber, |
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251 | 0, |
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252 | PCI_CONFIG_VENDOR_LOW, |
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253 | &ulDeviceID); |
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254 | if(ulDeviceID!=PCI_ID(0x1022, 0x2000)) |
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255 | { |
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256 | continue; |
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257 | } |
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258 | |
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259 | /* |
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260 | * We've found a PC-NET controller |
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261 | */ |
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262 | if(i++<instance) |
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263 | { |
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264 | continue; |
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265 | } |
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266 | |
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267 | /* |
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268 | * Read base address |
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269 | */ |
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270 | PCIConfigRead32(ucBusNumber, |
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271 | ucSlotNumber, |
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272 | 0, |
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273 | PCI_CONFIG_BAR_0, |
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274 | &ulBAR0); |
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275 | dp->pPCNet=(pc_net_t *)(ulBAR0&~PCI_ADDRESS_IO_SPACE); |
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276 | |
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277 | /* |
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278 | * Read interrupt vector |
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279 | */ |
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280 | PCIConfigRead8(ucBusNumber, |
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281 | ucSlotNumber, |
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282 | 0, |
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283 | PCI_CONFIG_INTERRUPTLINE, |
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284 | &ucIntVector); |
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285 | dp->ulIntVector=PPCN_60X_IRQ_PCI(ucIntVector); |
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286 | |
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287 | /* |
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288 | * Ensure that device is enabled |
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289 | */ |
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290 | PCIConfigWrite16(ucBusNumber, |
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291 | ucSlotNumber, |
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292 | 0, |
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293 | PCI_CONFIG_COMMAND, |
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294 | PCI_ENABLE_IO_SPACE | |
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295 | PCI_ENABLE_BUS_MASTER); |
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296 | break; |
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297 | } |
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298 | } |
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299 | |
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300 | if(dp->pPCNet==(pc_net_t *)NULL) |
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301 | { |
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302 | return(FALSE); |
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303 | } |
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304 | |
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305 | /* |
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306 | * Read the ethernet number |
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307 | */ |
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308 | if(!dp->iface->hwaddr) |
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309 | { |
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310 | dp->iface->hwaddr=mallocw (EADDR_LEN); |
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311 | PCNET_IO_RD32(dp, aprom[0], ulAPROM); |
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312 | for(i=0;i<4;i++) |
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313 | { |
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314 | dp->iface->hwaddr[i]=(ulAPROM>>(i*8))&0xff; |
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315 | } |
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316 | PCNET_IO_RD32(dp, aprom[1], ulAPROM); |
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317 | for(i=0;i<2;i++) |
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318 | { |
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319 | dp->iface->hwaddr[i+4]=(ulAPROM>>(i*8))&0xff; |
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320 | } |
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321 | } |
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322 | |
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323 | /* |
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324 | * Allocate mbuf pointers |
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325 | */ |
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326 | dp->rxMbuf=mallocw (dp->rxBdCount * sizeof(*dp->rxMbuf)); |
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327 | dp->txMbuf=mallocw (dp->txBdCount * sizeof(*dp->txMbuf)); |
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328 | |
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329 | /* |
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330 | * Allocate space for incoming packets |
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331 | */ |
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332 | for(i=0; i<dp->rxBdCount; i++) |
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333 | { |
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334 | dp->rxMbuf[i]=bp=ambufw (RBUF_SIZE); |
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335 | bp->data += sizeof (struct iface *); |
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336 | dp->rxBdBase[i].rmde_addr= |
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337 | Swap32((uint32_t)bp->data+PCI_SYS_MEM_BASE); |
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338 | dp->rxBdBase[i].rmde_bcnt= |
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339 | Swap16(-(bp->size-sizeof (struct iface *))); |
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340 | dp->rxBdBase[i].rmde_flags=Swap16(RFLG_OWN); |
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341 | } |
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342 | |
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343 | /* |
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344 | * Set up transmit buffer descriptors |
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345 | */ |
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346 | for(i=0; i<dp->txBdCount; i++) |
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347 | { |
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348 | dp->txBdBase[i].tmde_status=Swap16(TST_STP | TST_ENP); |
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349 | dp->txBdBase[i].tmde_error=0; |
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350 | dp->txMbuf[i]=NULL; |
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351 | } |
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352 | |
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353 | /* |
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354 | * Initialise initblk |
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355 | */ |
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356 | if(broadcastFlag) |
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357 | { |
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358 | dp->initBlk.ib_mode=0; |
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359 | } |
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360 | else |
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361 | { |
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362 | dp->initBlk.ib_mode=Swap16(CSR15_DRCVBC); |
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363 | } |
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364 | |
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365 | /* |
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366 | * Set the receive descriptor ring length |
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367 | */ |
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368 | dp->initBlk.ib_rlen=RX_RING_LEN_BITS; |
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369 | /* |
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370 | * Set the receive descriptor ring address |
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371 | */ |
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372 | dp->initBlk.ib_rdra=Swap32((uint32_t)&dp->rxBdBase[0]+ |
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373 | PCI_SYS_MEM_BASE); |
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374 | |
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375 | /* |
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376 | * Set the transmit descriptor ring length |
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377 | */ |
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378 | dp->initBlk.ib_tlen=TX_RING_LEN_BITS; |
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379 | /* |
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380 | * Set the tranmit descriptor ring address |
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381 | */ |
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382 | dp->initBlk.ib_tdra=Swap32((uint32_t)&dp->txBdBase[0]+ |
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383 | PCI_SYS_MEM_BASE); |
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384 | |
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385 | for(i=0;i<6;i++) |
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386 | { |
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387 | dp->initBlk.ib_padr[i]=dp->iface->hwaddr[i]; |
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388 | } |
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389 | |
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390 | /* |
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391 | * Ensure that we are in DWIO mode |
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392 | */ |
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393 | PCNET_IO_WR32(dp, rdp, 0); |
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394 | |
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395 | WR_CSR32(dp, 58,CSR58_PCISTYLE); |
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396 | |
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397 | WR_CSR32(dp, CSR3, |
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398 | CSR3_BABLM | CSR3_MERRM | CSR3_IDONM | CSR3_DXSUFLO); |
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399 | |
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400 | WR_CSR32(dp, CSR4, |
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401 | CSR4_APADXMIT | CSR4_MFCOM | CSR4_RCVCCOM | |
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402 | CSR4_TXSTRTM | CSR4_JABM); |
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403 | |
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404 | WR_CSR32(dp, CSR5, 0); |
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405 | |
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406 | ulInitClkPCIAddr=(uint32_t)&dp->initBlk+PCI_SYS_MEM_BASE; |
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407 | /* |
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408 | * CSR2 must contain the high order 16 bits of the first word in |
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409 | * the initialization block |
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410 | */ |
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411 | WR_CSR32(dp, CSR2, (ulInitClkPCIAddr >> 16) & 0xffff); |
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412 | /* |
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413 | * CSR1 must contain the low order 16 bits of the first word in |
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414 | * the initialization block |
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415 | */ |
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416 | WR_CSR32(dp, CSR1, (ulInitClkPCIAddr & 0xffff)); |
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417 | |
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418 | /* |
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419 | * Set up interrupts |
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420 | */ |
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421 | set_vector(amd79c970_isr, |
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422 | dp->ulIntVector, |
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423 | instance); |
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424 | |
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425 | /* |
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426 | * Start the device |
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427 | */ |
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428 | WR_CSR32(dp, CSR0, CSR0_INIT | CSR0_STRT); |
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429 | |
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430 | /* |
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431 | * Wait for 100mS for the device to initialise |
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432 | */ |
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433 | for(i=0; i<100; i++) |
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434 | { |
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435 | RD_CSR32(dp, CSR0, ulCSR0); |
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436 | if(ulCSR0 & CSR0_IDON) |
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437 | { |
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438 | break; |
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439 | } |
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440 | rtems_ka9q_ppause(1); /* 1mS */ |
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441 | } |
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442 | if(i >= 100) |
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443 | { |
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444 | return(FALSE); |
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445 | } |
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446 | |
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447 | /* |
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448 | * Enable interrupts |
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449 | */ |
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450 | WR_CSR32(dp, CSR0, CSR0_IENA); |
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451 | |
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452 | dp->txBdHead=dp->txBdTail=0; |
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453 | dp->txBdActiveCount=0; |
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454 | |
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455 | return(TRUE); |
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456 | } |
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457 | |
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458 | /* |
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459 | * Soak up buffer descriptors that have been sent |
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460 | */ |
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461 | static void |
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462 | amd79c970_retire_tx_bd (amd79c970Context_t *dp) |
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463 | { |
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464 | uint16_t status; |
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465 | uint32_t error; |
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466 | int i; |
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467 | int nRetired; |
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468 | |
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469 | i = dp->txBdTail; |
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470 | nRetired = 0; |
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471 | while((dp->txBdActiveCount != 0) && |
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472 | (((status=Swap16(dp->txBdBase[i].tmde_status)) & TST_OWN)==0)) |
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473 | { |
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474 | /* |
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475 | * See if anything went wrong |
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476 | */ |
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477 | if(status & TST_ERR) |
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478 | { |
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479 | /* |
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480 | * Check for errors |
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481 | */ |
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482 | error=Swap16(dp->txBdBase[i].tmde_error); |
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483 | |
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484 | if (error & TERR_LCOL) |
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485 | dp->txLateCollision++; |
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486 | if (error & TERR_RTRY) |
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487 | dp->txRetryLimit++; |
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488 | if (error & TERR_UFLO) |
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489 | dp->txUnderrun++; |
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490 | if (error & TERR_EXDEF) |
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491 | dp->txDeferred++; |
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492 | if (error & TERR_LCAR) |
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493 | dp->txLostCarrier++; |
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494 | } |
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495 | nRetired++; |
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496 | if (status & TST_ENP) |
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497 | { |
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498 | /* |
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499 | * A full frame has been transmitted. |
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500 | * Free all the associated buffer descriptors. |
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501 | */ |
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502 | dp->txBdActiveCount -= nRetired; |
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503 | while (nRetired) { |
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504 | nRetired--; |
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505 | free_mbuf (&dp->txMbuf[dp->txBdTail]); |
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506 | if (++dp->txBdTail == dp->txBdCount) |
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507 | dp->txBdTail = 0; |
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508 | } |
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509 | } |
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510 | if (++i == dp->txBdCount) |
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511 | { |
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512 | i = 0; |
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513 | } |
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514 | } |
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515 | } |
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516 | |
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517 | /* |
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518 | * Send raw packet (caller provides header). |
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519 | * This code runs in the context of the interface transmit |
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520 | * task or in the context of the network task. |
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521 | */ |
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522 | static int |
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523 | amd79c970_raw (struct iface *iface, struct mbuf **bpp) |
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524 | { |
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525 | amd79c970Context_t *dp; |
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526 | struct mbuf *bp; |
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527 | tmde_t *firstTxBd, *txBd; |
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528 | uint16_t status; |
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529 | int nAdded; |
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530 | |
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531 | dp = pAmd79c970Context[iface->dev]; |
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532 | |
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533 | /* |
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534 | * Fill in some logging data |
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535 | */ |
---|
536 | iface->rawsndcnt++; |
---|
537 | iface->lastsent = secclock (); |
---|
538 | dump (iface, IF_TRACE_OUT, *bpp); |
---|
539 | |
---|
540 | /* |
---|
541 | * It would not do to have two tasks active in the transmit |
---|
542 | * loop at the same time. |
---|
543 | * The blocking is simple-minded since the odds of two tasks |
---|
544 | * simultaneously attempting to use this code are low. The only |
---|
545 | * way that two tasks can try to run here is: |
---|
546 | * 1) Task A enters this code and ends up having to |
---|
547 | * wait for a transmit buffer descriptor. |
---|
548 | * 2) Task B gains control and tries to transmit a packet. |
---|
549 | * The RTEMS/KA9Q scheduling semaphore ensures that there |
---|
550 | * are no race conditions associated with manipulating the |
---|
551 | * txWaitTid variable. |
---|
552 | */ |
---|
553 | if (dp->txWaitTid) { |
---|
554 | dp->txRawWait++; |
---|
555 | while (dp->txWaitTid) |
---|
556 | rtems_ka9q_ppause (10); |
---|
557 | } |
---|
558 | |
---|
559 | /* |
---|
560 | * Free up buffer descriptors |
---|
561 | */ |
---|
562 | amd79c970_retire_tx_bd (dp); |
---|
563 | |
---|
564 | /* |
---|
565 | * Set up the transmit buffer descriptors. |
---|
566 | * No need to pad out short packets since the |
---|
567 | * hardware takes care of that automatically. |
---|
568 | * No need to copy the packet to a contiguous buffer |
---|
569 | * since the hardware is capable of scatter/gather DMA. |
---|
570 | */ |
---|
571 | bp = *bpp; |
---|
572 | nAdded = 0; |
---|
573 | txBd = firstTxBd = dp->txBdBase + dp->txBdHead; |
---|
574 | for (;;) { |
---|
575 | /* |
---|
576 | * Wait for buffer descriptor to become available. |
---|
577 | */ |
---|
578 | if ((dp->txBdActiveCount + nAdded) == dp->txBdCount) { |
---|
579 | /* |
---|
580 | * Find out who we are |
---|
581 | */ |
---|
582 | if (dp->txWaitTid == 0) |
---|
583 | rtems_task_ident (0, 0, &dp->txWaitTid); |
---|
584 | |
---|
585 | /* |
---|
586 | * Wait for buffer descriptor to become available. |
---|
587 | * Note that the buffer descriptors are checked |
---|
588 | * *before* * entering the wait loop -- this catches |
---|
589 | * the possibility that a buffer descriptor became |
---|
590 | * available between the `if' above, and the clearing |
---|
591 | * of the event register. |
---|
592 | * Also, the event receive doesn't wait forever. |
---|
593 | * This is to catch the case where the transmitter |
---|
594 | * stops in the middle of a frame -- and only the |
---|
595 | * last buffer descriptor in a frame can generate |
---|
596 | * an interrupt. |
---|
597 | */ |
---|
598 | amd79c970_retire_tx_bd (dp); |
---|
599 | while ((dp->txBdActiveCount + nAdded) == dp->txBdCount) { |
---|
600 | rtems_ka9q_event_receive (INTERRUPT_EVENT, |
---|
601 | RTEMS_WAIT|RTEMS_EVENT_ANY, |
---|
602 | 1 + 1000000/BSP_Configuration.microseconds_per_tick); |
---|
603 | amd79c970_retire_tx_bd (dp); |
---|
604 | } |
---|
605 | } |
---|
606 | |
---|
607 | /* |
---|
608 | * Fill in the buffer descriptor |
---|
609 | */ |
---|
610 | txBd->tmde_addr=Swap32((uint32_t)bp->data+PCI_SYS_MEM_BASE); |
---|
611 | txBd->tmde_bcnt=Swap16(-bp->cnt); |
---|
612 | dp->txMbuf[dp->txBdHead] = bp; |
---|
613 | |
---|
614 | nAdded++; |
---|
615 | if (++dp->txBdHead == dp->txBdCount) |
---|
616 | { |
---|
617 | dp->txBdHead = 0; |
---|
618 | } |
---|
619 | |
---|
620 | /* |
---|
621 | * Set the transmit buffer status. |
---|
622 | * Break out of the loop if this mbuf is the last in the frame. |
---|
623 | */ |
---|
624 | if ((bp = bp->next) == NULL) { |
---|
625 | if(txBd==firstTxBd) |
---|
626 | { |
---|
627 | /* |
---|
628 | * There is only one frame |
---|
629 | */ |
---|
630 | txBd->tmde_status=Swap16(TST_OWN | |
---|
631 | TST_STP | |
---|
632 | TST_ENP); |
---|
633 | } |
---|
634 | else |
---|
635 | { |
---|
636 | /* |
---|
637 | * Mark the last buffer |
---|
638 | */ |
---|
639 | txBd->tmde_status=Swap16(TST_OWN | |
---|
640 | TST_ENP); |
---|
641 | /* |
---|
642 | * Trigger the first transmit |
---|
643 | */ |
---|
644 | firstTxBd->tmde_status=Swap16(TST_OWN | |
---|
645 | TST_STP); |
---|
646 | } |
---|
647 | /* |
---|
648 | * Sync instruction required to overcome the Grackle |
---|
649 | * stale data bug |
---|
650 | */ |
---|
651 | asm volatile("sync"); |
---|
652 | dp->txBdActiveCount += nAdded; |
---|
653 | break; |
---|
654 | } |
---|
655 | else if(txBd!=firstTxBd) |
---|
656 | { |
---|
657 | txBd->tmde_status = Swap16(TST_OWN); |
---|
658 | } |
---|
659 | txBd = dp->txBdBase + dp->txBdHead; |
---|
660 | } |
---|
661 | |
---|
662 | /* |
---|
663 | * Show that we've finished with the packet |
---|
664 | */ |
---|
665 | dp->txWaitTid = 0; |
---|
666 | *bpp = NULL; |
---|
667 | return 0; |
---|
668 | } |
---|
669 | |
---|
670 | /* |
---|
671 | * PC-NET reader task |
---|
672 | */ |
---|
673 | static void |
---|
674 | amd79c970_rx (int dev, void *p1, void *p2) |
---|
675 | { |
---|
676 | struct iface *iface=(struct iface *)p1; |
---|
677 | amd79c970Context_t *dp=(amd79c970Context_t *)p2; |
---|
678 | struct mbuf *bp; |
---|
679 | uint16_t status; |
---|
680 | rmde_t *rxBd; |
---|
681 | int rxBdIndex; |
---|
682 | int continuousCount; |
---|
683 | |
---|
684 | /* |
---|
685 | * Input packet handling loop |
---|
686 | */ |
---|
687 | continuousCount=0; |
---|
688 | rxBdIndex=0; |
---|
689 | |
---|
690 | while(TRUE) |
---|
691 | { |
---|
692 | rxBd=&dp->rxBdBase[rxBdIndex]; |
---|
693 | |
---|
694 | /* |
---|
695 | * Wait for packet if there's not one ready |
---|
696 | */ |
---|
697 | if((status=Swap16(rxBd->rmde_flags)) & RFLG_OWN) |
---|
698 | { |
---|
699 | /* |
---|
700 | * Reset `continuous-packet' count |
---|
701 | */ |
---|
702 | continuousCount=0; |
---|
703 | |
---|
704 | /* |
---|
705 | * Wait for packet |
---|
706 | * Note that the buffer descriptor is checked |
---|
707 | * *before* the event wait -- this catches the |
---|
708 | * possibility that a packet arrived between the |
---|
709 | * `if' above, and the clearing of the event register. |
---|
710 | */ |
---|
711 | while ((status=Swap16(rxBd->rmde_flags)) & RFLG_OWN) |
---|
712 | { |
---|
713 | rtems_ka9q_event_receive (INTERRUPT_EVENT, |
---|
714 | RTEMS_WAIT|RTEMS_EVENT_ANY, |
---|
715 | RTEMS_NO_TIMEOUT); |
---|
716 | } |
---|
717 | } |
---|
718 | |
---|
719 | /* |
---|
720 | * Check that packet is valid |
---|
721 | */ |
---|
722 | if((status & RFLG_ERR) || |
---|
723 | ((status & (RFLG_STP|RFLG_ENP)) != (RFLG_STP|RFLG_ENP))) |
---|
724 | { |
---|
725 | /* |
---|
726 | * Something went wrong with the reception |
---|
727 | */ |
---|
728 | if(!(status & RFLG_ENP)) |
---|
729 | dp->rxNotLast++; |
---|
730 | if(!(status & RFLG_STP)) |
---|
731 | dp->rxNotFirst++; |
---|
732 | if(status & RFLG_OFLO) |
---|
733 | dp->rxGiant++; |
---|
734 | if(status & RFLG_FRAM) |
---|
735 | dp->rxNonOctet++; |
---|
736 | if(status & RFLG_CRC) |
---|
737 | dp->rxBadCRC++; |
---|
738 | if(status & RFLG_BUFF) |
---|
739 | dp->rxOverrun++; |
---|
740 | } |
---|
741 | else |
---|
742 | { |
---|
743 | /* |
---|
744 | * Pass the packet up the chain |
---|
745 | * The mbuf count is reduced to remove |
---|
746 | * the frame check sequence at the end |
---|
747 | * of the packet. |
---|
748 | */ |
---|
749 | bp=dp->rxMbuf[rxBdIndex]; |
---|
750 | bp->cnt=Swap16(rxBd->rmde_mcnt) - sizeof (uint32); |
---|
751 | net_route (iface, &bp); |
---|
752 | |
---|
753 | /* |
---|
754 | * Give the network code a chance to digest the |
---|
755 | * packet. This guards against a flurry of |
---|
756 | * incoming packets (usually an ARP storm) from |
---|
757 | * using up all the available memory. |
---|
758 | */ |
---|
759 | if(++continuousCount >= dp->rxBdCount) |
---|
760 | kwait_null (); |
---|
761 | |
---|
762 | /* |
---|
763 | * Allocate a new mbuf |
---|
764 | * FIXME: It seems to me that it would be better |
---|
765 | * if there were some way to limit number of mbufs |
---|
766 | * in use by this interface, but I don't see any |
---|
767 | * way of determining when the mbuf we pass up |
---|
768 | * is freed. |
---|
769 | */ |
---|
770 | dp->rxMbuf[rxBdIndex]=bp=ambufw (RBUF_SIZE); |
---|
771 | bp->data += sizeof (struct iface *); |
---|
772 | rxBd->rmde_addr=Swap32( |
---|
773 | (uint32_t)bp->data+PCI_SYS_MEM_BASE); |
---|
774 | rxBd->rmde_bcnt=Swap16( |
---|
775 | -(bp->size-sizeof (struct iface *))); |
---|
776 | } |
---|
777 | |
---|
778 | /* |
---|
779 | * Reenable the buffer descriptor |
---|
780 | */ |
---|
781 | rxBd->rmde_flags=Swap16(RFLG_OWN); |
---|
782 | |
---|
783 | /* |
---|
784 | * Move to next buffer descriptor |
---|
785 | */ |
---|
786 | if(++rxBdIndex==dp->rxBdCount) |
---|
787 | rxBdIndex=0; |
---|
788 | } |
---|
789 | } |
---|
790 | |
---|
791 | /* |
---|
792 | * Shut down the interface |
---|
793 | * FIXME: This is a pretty simple-minded routine. It doesn't worry |
---|
794 | * about cleaning up mbufs, shutting down daemons, etc. |
---|
795 | */ |
---|
796 | static int |
---|
797 | amd79c970_stop (struct iface *iface) |
---|
798 | { |
---|
799 | amd79c970Context_t *dp; |
---|
800 | uint32_t ulCSR0; |
---|
801 | int i; |
---|
802 | |
---|
803 | dp=pAmd79c970Context[iface->dev]; |
---|
804 | |
---|
805 | /* |
---|
806 | * Stop the device |
---|
807 | */ |
---|
808 | WR_CSR32(dp, CSR0, CSR0_STOP); |
---|
809 | |
---|
810 | /* |
---|
811 | * Wait for 100mS for the device to stop |
---|
812 | */ |
---|
813 | for(i=0; i<100; i++) |
---|
814 | { |
---|
815 | RD_CSR32(dp, CSR0, ulCSR0); |
---|
816 | if(!(ulCSR0 & (CSR0_RXON | CSR0_TXON))) |
---|
817 | { |
---|
818 | break; |
---|
819 | } |
---|
820 | rtems_ka9q_ppause(1); /* 1mS */ |
---|
821 | } |
---|
822 | if(i >= 100) |
---|
823 | { |
---|
824 | return(-1); |
---|
825 | } |
---|
826 | |
---|
827 | /* |
---|
828 | * Free up all the mbufs we've allocated |
---|
829 | */ |
---|
830 | for(i=0; i<dp->rxBdCount; i++) |
---|
831 | { |
---|
832 | free_mbuf(&dp->rxMbuf[i]); |
---|
833 | } |
---|
834 | |
---|
835 | return 0; |
---|
836 | } |
---|
837 | |
---|
838 | /* |
---|
839 | * Show interface statistics |
---|
840 | */ |
---|
841 | static void |
---|
842 | amd79c970_show (struct iface *iface) |
---|
843 | { |
---|
844 | int i; |
---|
845 | |
---|
846 | i=iface->dev; |
---|
847 | |
---|
848 | printf (" Rx Interrupts:%-8lu", pAmd79c970Context[i]->rxInterrupts); |
---|
849 | printf (" Not First:%-8lu", pAmd79c970Context[i]->rxNotFirst); |
---|
850 | printf (" Not Last:%-8lu\n", pAmd79c970Context[i]->rxNotLast); |
---|
851 | printf (" Giant:%-8lu", pAmd79c970Context[i]->rxGiant); |
---|
852 | printf (" Runt:%-8lu", pAmd79c970Context[i]->rxRunt); |
---|
853 | printf (" Non-octet:%-8lu\n", pAmd79c970Context[i]->rxNonOctet); |
---|
854 | printf (" Bad CRC:%-8lu", pAmd79c970Context[i]->rxBadCRC); |
---|
855 | printf (" Overrun:%-8lu", pAmd79c970Context[i]->rxOverrun); |
---|
856 | printf (" Collision:%-8lu\n", pAmd79c970Context[i]->rxCollision); |
---|
857 | printf (" Discarded:%-8lu\n", pAmd79c970Context[i]->rxDiscarded); |
---|
858 | |
---|
859 | printf (" Tx Interrupts:%-8lu", pAmd79c970Context[i]->txInterrupts); |
---|
860 | printf (" Deferred:%-8lu", pAmd79c970Context[i]->txDeferred); |
---|
861 | printf (" Missed Hearbeat:%-8lu\n", pAmd79c970Context[i]->txHeartbeat); |
---|
862 | printf (" No Carrier:%-8lu", pAmd79c970Context[i]->txLostCarrier); |
---|
863 | printf ("Retransmit Limit:%-8lu", pAmd79c970Context[i]->txRetryLimit); |
---|
864 | printf (" Late Collision:%-8lu\n", pAmd79c970Context[i]->txLateCollision); |
---|
865 | printf (" Underrun:%-8lu", pAmd79c970Context[i]->txUnderrun); |
---|
866 | printf (" Raw output wait:%-8lu\n", pAmd79c970Context[i]->txRawWait); |
---|
867 | } |
---|
868 | |
---|
869 | /* |
---|
870 | * Attach an PC-NET driver to the system |
---|
871 | * This is the only `extern' function in the driver. |
---|
872 | * |
---|
873 | * argv[0]: interface label, e.g., "amd79c970" |
---|
874 | * argv[1]: maximum transmission unit, bytes, e.g., "1500" |
---|
875 | * argv[2]: accept ("broadcast") or ignore ("nobroadcast") broadcast packets |
---|
876 | * Following arguments are optional, but if present, must appear in |
---|
877 | * the following order: |
---|
878 | * Following arguments are optional, but if Ethernet address is |
---|
879 | * specified, Internet address must also be specified. |
---|
880 | * ###.###.###.### -- IP address |
---|
881 | * ##:##:##:##:##:## -- Ethernet address |
---|
882 | */ |
---|
883 | int |
---|
884 | rtems_ka9q_driver_attach (int argc, char *argv[], void *p) |
---|
885 | { |
---|
886 | struct iface *iface; |
---|
887 | struct amd79c970Context *dp; |
---|
888 | char *cp; |
---|
889 | int i; |
---|
890 | int argIndex; |
---|
891 | int broadcastFlag; |
---|
892 | |
---|
893 | /* |
---|
894 | * Find a free driver |
---|
895 | */ |
---|
896 | for(i=0; i<NPCNETDRIVER; i++) |
---|
897 | { |
---|
898 | if(pAmd79c970Context[i]==NULL) |
---|
899 | break; |
---|
900 | } |
---|
901 | if(i==NPCNETDRIVER) |
---|
902 | { |
---|
903 | printf ("Too many PC-NET drivers.\n"); |
---|
904 | return -1; |
---|
905 | } |
---|
906 | if(if_lookup (argv[0]) != NULL) |
---|
907 | { |
---|
908 | printf ("Interface %s already exists\n", argv[0]); |
---|
909 | return -1; |
---|
910 | } |
---|
911 | |
---|
912 | /* |
---|
913 | * Note that this structure must be aligned to a 16 byte boundary |
---|
914 | */ |
---|
915 | pAmd79c970Context[i]=(amd79c970Context_t *) |
---|
916 | (((uint32_t)callocw(1, |
---|
917 | sizeof(amd79c970Context_t)+16)+16) & ~15); |
---|
918 | dp=pAmd79c970Context[i]; |
---|
919 | |
---|
920 | /* |
---|
921 | * Create an interface descriptor |
---|
922 | */ |
---|
923 | iface=callocw (1, sizeof *iface); |
---|
924 | iface->name=strdup (argv[0]); |
---|
925 | iface->mtu=atoi (argv[1]); |
---|
926 | |
---|
927 | /* |
---|
928 | * Select broadcast packet handling |
---|
929 | */ |
---|
930 | cp=argv[2]; |
---|
931 | if(strnicmp (cp, "broadcast", strlen (cp))==0) |
---|
932 | { |
---|
933 | broadcastFlag=1; |
---|
934 | } |
---|
935 | else if(strnicmp (cp, "nobroadcast", strlen (cp))==0) |
---|
936 | { |
---|
937 | broadcastFlag=0; |
---|
938 | } |
---|
939 | else { |
---|
940 | printf ("Argument `%s' is neither `broadcast' nor `nobroadcast'.\n", cp); |
---|
941 | return -1; |
---|
942 | } |
---|
943 | argIndex=3; |
---|
944 | |
---|
945 | /* |
---|
946 | * Set receive buffer descriptor count |
---|
947 | */ |
---|
948 | dp->rxBdCount=RX_RING_SIZE; |
---|
949 | |
---|
950 | /* |
---|
951 | * Set transmit buffer descriptor count |
---|
952 | */ |
---|
953 | dp->txWaitTid=0; |
---|
954 | dp->txBdCount=TX_RING_SIZE; |
---|
955 | |
---|
956 | /* |
---|
957 | * Set Internet address |
---|
958 | */ |
---|
959 | if(argIndex<argc) |
---|
960 | iface->addr=resolve (argv[argIndex++]); |
---|
961 | else |
---|
962 | iface->addr=Ip_addr; |
---|
963 | |
---|
964 | /* |
---|
965 | * Set Ethernet address |
---|
966 | */ |
---|
967 | if(argIndex<argc) |
---|
968 | { |
---|
969 | iface->hwaddr=mallocw (EADDR_LEN); |
---|
970 | gether (iface->hwaddr, argv[argIndex++]); |
---|
971 | } |
---|
972 | |
---|
973 | iface->dev=i; |
---|
974 | iface->raw=amd79c970_raw; |
---|
975 | iface->stop=amd79c970_stop; |
---|
976 | iface->show=amd79c970_show; |
---|
977 | dp->iface=iface; |
---|
978 | setencap (iface, "Ethernet"); |
---|
979 | |
---|
980 | /* |
---|
981 | * Set up PC-NET hardware |
---|
982 | */ |
---|
983 | if(!amd79c970_initialize_hardware (i, broadcastFlag)) |
---|
984 | { |
---|
985 | printf ("Unable to initialize hardware for %s\n", argv[0]); |
---|
986 | return -1; |
---|
987 | } |
---|
988 | |
---|
989 | /* |
---|
990 | * Chain onto list of interfaces |
---|
991 | */ |
---|
992 | iface->next=Ifaces; |
---|
993 | Ifaces=iface; |
---|
994 | |
---|
995 | /* |
---|
996 | * Start I/O daemons |
---|
997 | */ |
---|
998 | cp=if_name (iface, " tx"); |
---|
999 | iface->txproc=newproc (cp, 1024, if_tx, iface->dev, iface, NULL, 0); |
---|
1000 | free (cp); |
---|
1001 | cp=if_name (iface, " rx"); |
---|
1002 | iface->rxproc=newproc (cp, 1024, amd79c970_rx, iface->dev, iface, dp, 0); |
---|
1003 | free (cp); |
---|
1004 | return 0; |
---|
1005 | } |
---|
1006 | |
---|
1007 | /* |
---|
1008 | * FIXME: There should be an ioctl routine to allow things like |
---|
1009 | * enabling/disabling reception of broadcast packets. |
---|
1010 | */ |
---|