source: rtems/c/src/lib/libbsp/powerpc/ppcn_60x/include/pci.h @ eba2e4f

4.104.114.84.95
Last change on this file since eba2e4f was 0c04c377, checked in by Joel Sherrill <joel.sherrill@…>, on 02/18/99 at 16:48:14

./clock/Makefile.in,v
./clock/clock.c,v
./console/Makefile.in,v
./console/config.c,v
./console/console.c,v
./console/console.h,v
./console/debugio.c,v
./console/i8042.c,v
./console/i8042_p.h,v
./console/i8042vga.c,v
./console/i8042vga.h,v
./console/ns16550.c,v
./console/ns16550.h,v
./console/ns16550_p.h,v
./console/ns16550cfg.c,v
./console/ns16550cfg.h,v
./console/vga.c,v
./console/vga_p.h,v
./console/z85c30.c,v
./console/z85c30.h,v
./console/z85c30_p.h,v
./console/z85c30cfg.c,v
./console/z85c30cfg.h,v
./include/Makefile.in,v
./include/bsp.h,v
./include/chain.h,v
./include/coverhd.h,v
./include/extisrdrv.h,v
./include/nvram.h,v
./include/pci.h,v
./include/tod.h,v
./network/Makefile.in,v
./network/amd79c970.c,v
./network/amd79c970.h,v
./nvram/Makefile.in,v
./nvram/ds1385.h,v
./nvram/mk48t18.h,v
./nvram/nvram.c,v
./nvram/prepnvr.h,v
./nvram/stk11c68.h,v
./pci/Makefile.in,v
./pci/pci.c,v
./start/Makefile.in,v
./start/start.s,v
./startup/Makefile.in,v
./startup/bspclean.c,v
./startup/bspstart.c,v
./startup/bsptrap.s,v
./startup/device-tree,v
./startup/genpvec.c,v
./startup/linkcmds,v
./startup/rtems-ctor.cc,v
./startup/sbrk.c,v
./startup/setvec.c,v
./startup/spurious.c,v
./startup/swap.c,v
./timer/Makefile.in,v
./timer/timer.c,v
./tod/Makefile.in,v
./tod/cmos.h,v
./tod/tod.c,v
./universe/Makefile.in,v
./universe/universe.c,v
./vectors/Makefile.in,v
./vectors/README,v
./vectors/align_h.s,v
./vectors/vectors.s,v
./wrapup/Makefile.in,v
./Makefile.in,v
./README,v
./STATUS,v
./bsp_specs,v
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1/*
2 *  COPYRIGHT (c) 1998 by Radstone Technology
3 *
4 *
5 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
6 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
7 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
8 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
9 *
10 * You are hereby granted permission to use, copy, modify, and distribute
11 * this file, provided that this notice, plus the above copyright notice
12 * and disclaimer, appears in all copies. Radstone Technology will provide
13 * no support for this code.
14 *
15 */
16#ifndef _PCI_H_
17#define _PCI_H_
18
19/*
20 * PCI Configuration space definitions
21 */
22
23#define PCI_CONFIG_ADDR 0xcf8
24#define PCI_CONFIG_DATA 0xcfc
25
26#define PCI_MAX_DEVICES         16
27#define PCI_MAX_FUNCTIONS       8
28
29#define PCI_CONFIG_VENDOR_LOW           0x00
30#define PCI_CONFIG_VENDOR_HIGH          0x01
31#define PCI_CONFIG_DEVICE_LOW           0x02
32#define PCI_CONFIG_DEVICE_HIGH          0x03
33#define PCI_CONFIG_COMMAND              0x04
34#define PCI_CONFIG_STATUS               0x06
35#define PCI_CONFIG_REVISIONID           0x08
36#define PCI_CONFIG_CLASS_CODE_L         0x09
37#define PCI_CONFIG_CLASS_CODE_M         0x0a
38#define PCI_CONFIG_CLASS_CODE_U         0x0b
39#define PCI_CONFIG_CACHE_LINE_SIZE      0x0c
40#define PCI_CONFIG_LATENCY_TIMER        0x0d
41#define PCI_CONFIG_HEADER_TYPE          0x0e
42#define PCI_CONFIG_BIST                 0x0f
43#define PCI_CONFIG_BAR_0                0x10
44#define PCI_CONFIG_BAR_1                0x14
45#define PCI_CONFIG_BAR_2                0x18
46#define PCI_CONFIG_BAR_3                0x1c
47#define PCI_CONFIG_BAR_4                0x20
48#define PCI_CONFIG_BAR_5                0x24
49#define PCI_CONFIG_SUBVENDOR_LOW        0x2c
50#define PCI_CONFIG_SUBVENDOR_HIGH       0x2d
51#define PCI_CONFIG_SUBDEVICE_LOW        0x2e
52#define PCI_CONFIG_SUBDEVICE_HIGH       0x2f
53#define PCI_CONFIG_ROM_BAR              0x30
54#define PCI_CONFIG_INTERRUPTLINE        0x3c
55#define PCI_CONFIG_INTERRUPTPIN         0x3d
56#define PCI_CONFIG_MIN_GNT              0x3e
57#define PCI_CONFIG_MAX_LAT              0x3f
58
59/*
60 * PCI Status register definitions
61 */
62
63#define PCI_STATUS_66MHZ_CAPABLE        0x0020
64#define PCI_STATUS_UDF_SUPPORTED        0x0040
65#define PCI_STATUS_FAST_BACK_TO_BACK    0x0080
66#define PCI_STATUS_DET_DPAR_ERR         0x0100
67#define PCI_STATUS_DEVSEL_MSK           0x0600
68#define PCI_STATUS_DEVSEL_SLOW          0x0400
69#define PCI_STATUS_DEVSEL_MED           0x0200
70#define PCI_STATUS_DEVSEL_FAST          0x0000
71#define PCI_STATUS_SIG_TARG_ABT         0x0800
72#define PCI_STATUS_REC_TARG_ABT         0x1000
73#define PCI_STATUS_REC_MAST_ABT         0x2000
74#define PCI_STATUS_SIG_SYS_ERR          0x4000
75#define PCI_STATUS_DET_PAR_ERR          0x8000
76
77/*
78 * PCI Enable register definitions
79 */
80
81#define PCI_ENABLE_IO_SPACE             0x0001
82#define PCI_ENABLE_MEMORY_SPACE         0x0002
83#define PCI_ENABLE_BUS_MASTER           0x0004
84#define PCI_ENABLE_SPECIAL_CYCLES       0x0008
85#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
86#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
87#define PCI_ENABLE_PARITY               0x0040
88#define PCI_ENABLE_WAIT_CYCLE           0x0080
89#define PCI_ENABLE_SERR                 0x0100
90#define PCI_ENABLE_FAST_BACK_TO_BACK    0x0200
91
92/*
93 * Bit encode for PCI_CONFIG_HEADER_TYPE register
94 */
95
96#define PCI_MULTI_FUNCTION      0x80
97
98/*
99 * Bit encodes for PCI Config BaseAddressesRegisters (BARs)
100 */
101
102#define PCI_ADDRESS_IO_SPACE                0x00000001
103#define PCI_ADDRESS_MEMORY_TYPE_MASK        0x00000007
104#define PCI_ADDRESS_MEMORY_PREFETCHABLE     0x00000008
105
106#define PCI_TYPE_32BIT      0
107#define PCI_TYPE_20BIT      2
108#define PCI_TYPE_64BIT      4
109
110/*
111 * Bit encodes for PCI Config ROMBaseAddresses
112 */
113
114#define PCI_ROMADDRESS_ENABLED              0x00000001
115
116/*
117 * PCI Bridge Configuration space definitions
118 */
119
120#define PCI_BRIDGE_PRIMARY_BUS          0x18
121#define PCI_BRIDGE_SECONDARY_BUS        0x19
122#define PCI_BRIDGE_SUBORDINATE_BUS      0x1a
123#define PCI_BRIDGE_SECONDARY_LAT        0x1b
124#define PCI_BRIDGE_IO_BASE              0x1c
125#define PCI_BRIDGE_IO_LIMIT             0x1d
126#define PCI_BRIDGE_SECONDARY_STATUS     0x1e
127#define PCI_BRIDGE_MEMORY_BASE          0x20
128#define PCI_BRIDGE_MEMORY_LIMIT         0x22
129#define PCI_BRIDGE_PRE_MEMORY_BASE      0x24
130#define PCI_BRIDGE_PRE_MEMORY_LIMIT     0x26
131#define PCI_BRIDGE_PRE_BASE_U           0x28
132#define PCI_BRIDGE_PRE_LIMIT_U          0x2c
133#define PCI_BRIDGE_IO_BASE_U            0x30
134#define PCI_BRIDGE_IO_LIMIT_U           0x32
135#define PCI_BRIDGE_ROM_BAR              0x38
136#define PCI_BRIDGE_CONTROL              0x3e
137
138/*
139 * PCI Bridge Control register definitions
140 */
141
142#define PCI_BRIDGE_PAR_ERR_RESPONSE     0x01
143#define PCI_BRIDGE_S_SERR_L_FWD_EN      0x02
144#define PCI_BRIDGE_ENABLE_ISA           0x04
145#define PCI_BRIDGE_ENABLE_VGA           0x08
146#define PCI_BRIDGE_MASTER_ABORT         0x20
147#define PCI_BRIDGE_SECONDARY_RESET      0x40
148#define PCI_BRIDGE_BACK_TO_BACK_EN      0x80
149
150/*
151 * PCI IO address forwarding capability
152 */
153#define PCI_BRIDGE_IO_CAPABILITY        0x0f
154#define PCI_BRIDGE_IO_16BIT             0x00
155#define PCI_BRIDGE_IO_32BIT             0x01
156
157/*
158 * Class codes
159 */
160#define PCI_BASE_CLASS_NULL                     0x00
161#define PCI_BASE_CLASS_STORAGE          0x01
162#define PCI_BASE_CLASS_NETWORK          0x02
163#define PCI_BASE_CLASS_DISPLAY          0x03
164#define PCI_BASE_CLASS_MULTIMEDIA       0x04
165#define PCI_BASE_CLASS_MEMORY           0x05
166#define PCI_BASE_CLASS_BRIDGE           0x06
167#define PCI_BASE_CLASS_COM_CTRL         0x07
168#define PCI_BASE_CLASS_BASEPERIPH       0x08
169#define PCI_BASE_CLASS_INPUTDEV         0x09
170#define PCI_BASE_CLASS_DOCKING          0x0a
171#define PCI_BASE_CLASS_PROC                     0x0b
172#define PCI_BASE_CLASS_SERBUSCTRL       0x0c
173#define PCI_BASE_CLASS_UNDEFINED        0xff
174
175#define PCI_SUB_CLASS_NULL_NVGA         0x00
176#define PCI_IF_CLASS_DISPLAY_VGA                0x00
177#define PCI_IF_CLASS_DISPLAY_VGA8514    0x01
178#define PCI_SUB_CLASS_NULL_VGA          0x01
179
180#define PCI_SUB_CLASS_STORAGE_SCSI              0x00
181#define PCI_SUB_CLASS_STORAGE_IDE               0x01
182#define PCI_SUB_CLASS_STORAGE_FLOPPY    0x02
183#define PCI_SUB_CLASS_STORAGE_IPI               0x03
184#define PCI_SUB_CLASS_STORAGE_RAID              0x04
185#define PCI_SUB_CLASS_STORAGE_OTHER             0x80
186
187#define PCI_SUB_CLASS_NETWORK_ETH               0x00
188#define PCI_SUB_CLASS_NETWORK_TOKEN             0x01
189#define PCI_SUB_CLASS_NETWORK_FDDI              0x02
190#define PCI_SUB_CLASS_NETWORK_ATM               0x03
191#define PCI_SUB_CLASS_NETWORK_OTHER             0x80
192
193#define PCI_SUB_CLASS_DISPLAY_VGA               0x00
194#define PCI_SUB_CLASS_DISPLAY_XGA               0x01
195#define PCI_SUB_CLASS_DISPLAY_OTHER             0x80
196
197#define PCI_SUB_CLASS_MULTIMEDIA_VIDEO  0x00
198#define PCI_SUB_CLASS_MULTIMEDIA_AUDIO  0x01
199#define PCI_SUB_CLASS_MULTIMEDIA_OTHER  0x80
200
201#define PCI_SUB_CLASS_MEMORY_RAM                0x00
202#define PCI_SUB_CLASS_MEMORY_FLASH              0x01
203#define PCI_SUB_CLASS_MEMORY_OTHER              0x80
204
205#define PCI_SUB_CLASS_BRIDGE_HOST               0x00
206#define PCI_SUB_CLASS_BRIDGE_ISA                0x01
207#define PCI_SUB_CLASS_BRIDGE_EISA               0x02
208#define PCI_SUB_CLASS_BRIDGE_MC                 0x03
209#define PCI_SUB_CLASS_BRIDGE_PCI                0x04
210#define PCI_SUB_CLASS_BRIDGE_PCMCIA             0x05
211#define PCI_SUB_CLASS_BRIDGE_NUBUS              0x06
212#define PCI_SUB_CLASS_BRIDGE_CARDBUS    0x07
213#define PCI_SUB_CLASS_BRIDGE_OTHER              0x80
214
215#define PCI_SUB_CLASS_COM_CTRL_SERIAL   0x00
216#define PCI_IF_CLASS_COM_SER_XT                 0x00
217#define PCI_IF_CLASS_COM_SER_16450              0x01
218#define PCI_IF_CLASS_COM_SER_16550              0x02
219#define PCI_SUB_CLASS_COM_CTRL_PARALLEL 0x01
220#define PCI_IF_CLASS_COM_PAR                    0x00
221#define PCI_IF_CLASS_COM_PAR_BI                 0x01
222#define PCI_IF_CLASS_COM_PAR_ECP                0x02
223#define PCI_SUB_CLASS_COM_CTRL_OTHER    0x80
224
225#define PCI_SUB_CLASS_BASEPERIPH_PIC            0x00
226#define PCI_IF_CLASS_BASEPERIPH_PIC                     0x00
227#define PCI_IF_CLASS_BASEPERIPH_PIC_ISA         0x01
228#define PCI_IF_CLASS_BASEPERIPH_PIC_EISA        0x02
229#define PCI_SUB_CLASS_BASEPERIPH_DMA            0x01
230#define PCI_IF_CLASS_BASEPERIPH_DMA                     0x00
231#define PCI_IF_CLASS_BASEPERIPH_DMA_ISA         0x01
232#define PCI_IF_CLASS_BASEPERIPH_DMA_EISA        0x02
233#define PCI_SUB_CLASS_BASEPERIPH_TIMER          0x02
234#define PCI_IF_CLASS_BASEPERIPH_TIMER           0x00
235#define PCI_IF_CLASS_BASEPERIPH_TIMER_ISA       0x01
236#define PCI_IF_CLASS_BASEPERIPH_TIMER_EISA      0x02
237#define PCI_SUB_CLASS_BASEPERIPH_RTC            0x03
238#define PCI_IF_CLASS_BASEPERIPH_RTC                     0x00
239#define PCI_IF_CLASS_BASEPERIPH_RTC_ISA         0x01
240#define PCI_SUB_CLASS_BASEPERIPH_OTHER          0x80
241
242#define PCI_SUB_CLASS_INPUTDEV_KEYBOARD 0x00
243#define PCI_SUB_CLASS_INPUTDEV_PEN              0x01
244#define PCI_SUB_CLASS_INPUTDEV_MOUSE    0x02
245#define PCI_SUB_CLASS_INPUTDEV_OTHER    0x80
246
247#define PCI_SUB_CLASS_DOCKING_GENERIC   0x00
248#define PCI_SUB_CLASS_DOCKING_OTHER             0x80
249
250#define PCI_SUB_CLASS_PROC_386                  0x00
251#define PCI_SUB_CLASS_PROC_486                  0x01
252#define PCI_SUB_CLASS_PROC_PENTIUM              0x02
253#define PCI_SUB_CLASS_PROC_ALPHA                0x10
254#define PCI_SUB_CLASS_PROC_POWERPC              0x20
255#define PCI_SUB_CLASS_PROC_COPROC               0x40
256
257#define PCI_SUB_CLASS_SERBUSCTRL_FIREWIRE       0x00
258#define PCI_SUB_CLASS_SERBUSCTRL_ACCESS         0x01
259#define PCI_SUB_CLASS_SERBUSCTRL_SSA            0x02
260#define PCI_SUB_CLASS_SERBUSCTRL_USB            0x03
261#define PCI_SUB_CLASS_SERBUSCTRL_FIBRECHAN      0x04
262
263#define PCI_INVALID_VENDORDEVICEID      0xffffffff
264#define PCI_ID(v, d) ((d << 16) | v)
265
266/*
267 * PCI access functions
268 */
269extern rtems_status_code PCIConfigWrite8(
270    unsigned8 ucBusNumber,
271    unsigned8 ucSlotNumber,
272    unsigned8 ucFunctionNumber,
273    unsigned8 ucOffset,
274    unsigned8 ucValue
275);
276
277extern rtems_status_code PCIConfigWrite16(
278    unsigned8 ucBusNumber,
279    unsigned8 ucSlotNumber,
280    unsigned8 ucFunctionNumber,
281    unsigned8 ucOffset,
282    unsigned16 usValue
283);
284
285extern rtems_status_code PCIConfigWrite32(
286    unsigned8 ucBusNumber,
287    unsigned8 ucSlotNumber,
288    unsigned8 ucFunctionNumber,
289    unsigned8 ucOffset,
290    unsigned32 ulValue
291);
292
293extern rtems_status_code PCIConfigRead8(
294    unsigned8 ucBusNumber,
295    unsigned8 ucSlotNumber,
296    unsigned8 ucFunctionNumber,
297    unsigned8 ucOffset,
298    unsigned8 *pucValue
299);
300
301extern rtems_status_code PCIConfigRead16(
302    unsigned8 ucBusNumber,
303    unsigned8 ucSlotNumber,
304    unsigned8 ucFunctionNumber,
305    unsigned8 ucOffset,
306    unsigned16 *pusValue
307);
308
309extern rtems_status_code PCIConfigRead32(
310    unsigned8 ucBusNumber,
311    unsigned8 ucSlotNumber,
312    unsigned8 ucFunctionNumber,
313    unsigned8 ucOffset,
314    unsigned32 *pulValue
315);
316
317/*
318 * Return the number of PCI busses in the system
319 */
320extern unsigned8 BusCountPCI();
321
322#endif /* _PCI_H_ */
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