source: rtems/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h @ bad8092c

4.104.114.84.95
Last change on this file since bad8092c was bad8092c, checked in by Ralf Corsepius <ralf.corsepius@…>, on 03/31/04 at 03:49:17

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

  • clock/clock.c, console/config.c, console/console.c, console/debugio.c, console/i8042.c, console/ns16550cfg.c, console/ns16550cfg.h, console/vga.c, console/vga_p.h, console/z85c30cfg.c, console/z85c30cfg.h, include/bsp.h, include/nvram.h, include/pci.h, network/amd79c970.c, network/amd79c970.h, nvram/mk48t18.h, nvram/nvram.c, nvram/stk11c68.h, pci/pci.c, startup/bspstart.c, startup/genpvec.c, startup/spurious.c, startup/swap.c, timer/timer.c, tod/cmos.h, tod/tod.c, universe/universe.c: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 12.1 KB
Line 
1/*  bsp.h
2 *
3 *  This include file contains all board IO definitions.
4 *
5 *  COPYRIGHT (c) 1998 by Radstone Technology
6 *
7 *
8 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
9 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
10 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
11 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
12 *
13 * You are hereby granted permission to use, copy, modify, and distribute
14 * this file, provided that this notice, plus the above copyright notice
15 * and disclaimer, appears in all copies. Radstone Technology will provide
16 * no support for this code.
17 *
18 *  COPYRIGHT (c) 1989-1997.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may in
22 *  the file LICENSE in this distribution or at
23 *  http:www.OARcorp.com/rtems/license.html.
24 *
25 *  $Id$
26 */
27
28#ifndef __BSP_h
29#define __BSP_h
30
31#include <bspopts.h>
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37/*
38 *  confdefs.h overrides for this BSP:
39 *   - termios serial ports (defaults to 1)
40 *   - Interrupt stack space is not minimum if defined.
41 */
42
43#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
44#define CONFIGURE_INTERRUPT_STACK_MEMORY  (32 * 1024)
45 
46/*  Define processor identification. */
47
48#define MPC601  1
49#define MPC603  3
50#define MPC604  4
51#define MPC603e 6
52#define MPC603ev 7
53#define MPC604e 9
54
55#ifdef ASM
56/* Definition of where to store registers in alignment handler */
57#define ALIGN_REGS 0x0140
58
59/*  BAT register definitions for the MPC603 and MPC604. */
60/*  Define bit fields for upper MPC603/4 BAT registers. */
61
62#define BEPI_FIELD_60X      0xFFFE0000
63#define VALID_SUPERVISOR    0x2
64#define VALID_PROBLEM       0x1
65#define KEY_USER_60X        0x1
66#define BL_128K        0x0
67#define BL_256K        (0x1<2)
68#define BL_512K        (0x3<2)
69#define BL_1M          (0x7<2)
70#define BL_2M          (0xF<2)
71#define BL_4M          (0x1F<2)
72#define BL_8M          (0x3F<2)
73#define BL_16M         (0x7F<2)
74#define BL_32M         (0xFF<2)
75#define BL_64M         (0x1FF<2)
76#define BL_128M        (0x3FF<2)
77#define BL_256M        (0x7FF<2)
78
79
80/*  Define bit fields for lower MPC603/4 BAT registers. */
81
82#define BRPN_FIELD_60X      0xFFFE0000
83
84/*  Common defines for BAT registers. */
85/*  Depending on the processor, the following may be in the upper */
86/*  and lower BAT register. */
87
88#define WRITE_THRU      0x40
89#define WRITE_BK        0x0
90#define COHERE_EN       0x10
91#define COHERE_DIS      0x0
92#define CACHE_DIS       0x20
93#define CACHE_EN        0x0
94#define GUARDED_EN      0x8
95#define GUARDED_DIS     0x0
96#define PP_00           0x0
97#define PP_01           0x1
98#define PP_10           0x2
99#define PP_11           0x3
100
101/*  HID0 definitions for MPC603 and MPC604 */
102#define HID0            0x3f0      /*  HID0 Special Purpose Register # */
103/*  HID1 definitions for MPC603e and MPC604e */
104#define HID1            0x3f1      /*  HID1 Special Purpose Register # */
105
106#define H0_603_ICFI     0x0800     /*  HID0 I-Cache Flash Invalidate */
107#define H0_603_DCI      0x0400     /*  HID0 D-Cache Flash Invalidate */
108
109#define H0_60X_ICE      0x8000     /*  HID0 I-Cache Enable */
110#define H0_60X_DCE      0x4000     /*  HID0 D-Cache Enable */
111
112#define H0_604_BHTE     0x0004     /*  HID0 Branch History Table enable */
113#define H0_604_SIED     0x0080     /*  HID0 Serial Instruction Execution */
114#define H0_604_ICIA     0x0800     /*  HID0 I-Cache Invalidate All */
115#define H0_604_DCIA     0x0400     /*  HID0 D-Cache Invalidate All */
116
117#define BAT0U           528
118#define BAT0L           529
119#define BAT1U           530
120#define BAT1L           531
121#define BAT2U           532
122#define BAT2L           533
123#define BAT3U           534
124#define BAT3L           535
125#define SPRG0           272
126#define SPRG1           273
127
128/* MSR bit settings */
129#define MSR_LE          0x0001
130#define MSR_RI          0x0002
131#define MSR_DR          0x0010
132#define MSR_IR          0x0020
133#define MSR_IP          0x0040
134#define MSR_FE1         0x0100
135#define MSR_BE          0x0200
136#define MSR_SE          0x0400
137#define MSR_FE0         0x0800
138#define MSR_ME          0x1000
139#define MSR_FP          0x2000
140#define MSR_PR          0x4000
141#define MSR_EE          0x8000
142#define MSR_ILE         0x0001  /* Upper 16 bits */
143#define MSR_POW         0x0004  /* Upper 16 bits */
144#else
145#include <rtems.h>
146#include <console.h>
147#include <clockdrv.h>
148#include <iosupp.h>
149#include <tod.h>
150#include <nvram.h>
151
152/*
153 *  PPCn_60x Interupt Definations.
154 */
155#define PPCN_60X_8259_IRQ_BASE ( PPC_IRQ_LAST +  1 )
156
157/*
158 * 8259 IRQ definations.
159 */
160#define PPCN_60X_IRQ_SYS_TIMER  (PPCN_60X_8259_IRQ_BASE +  0) 
161#define PPCN_60X_IRQ_KBD                (PPCN_60X_8259_IRQ_BASE +  1) 
162#define PPCN_60X_IRQ_COM2               (PPCN_60X_8259_IRQ_BASE +  3)
163#define PPCN_60X_IRQ_COM1               (PPCN_60X_8259_IRQ_BASE +  4)
164#define PPCN_60X_IRQ_CIO                (PPCN_60X_8259_IRQ_BASE +  5)
165#define PPCN_60X_IRQ_FDC                (PPCN_60X_8259_IRQ_BASE +  6)
166#define PPCN_60X_IRQ_LPT                (PPCN_60X_8259_IRQ_BASE +  7)
167#define PPCN_60X_IRQ_RTC                (PPCN_60X_8259_IRQ_BASE +  8)
168#define PPCN_60X_IRQ_COM3_4             (PPCN_60X_8259_IRQ_BASE + 10)
169#define PPCN_60X_IRQ_MSE                (PPCN_60X_8259_IRQ_BASE + 12)
170#define PPCN_60X_IRQ_SCSI               (PPCN_60X_8259_IRQ_BASE + 13)
171
172/*
173 * PCI interrupts as read from line register map directly to
174 * ISA interrupt lines 9, 11, 14 and 15.
175 */
176#define PPCN_60X_IRQ_PCI(n)             (PPCN_60X_8259_IRQ_BASE +  (n))
177
178#define MAX_BOARD_IRQS          (PPCN_60X_8259_IRQ_BASE + 15)
179
180#define ISA8259_M_CTRL 0x20
181#define ISA8259_S_CTRL 0xa0
182#define ISA8259_M_MASK 0x21
183#define ISA8259_S_MASK 0xa1
184#define ISA8259_M_ELCR 0x4d0
185#define ISA8259_S_ELCR 0x4d1
186
187#define ELCRS_INT15_LVL         0x80
188#define ELCRS_INT14_LVL         0x40
189#define ELCRS_INT12_LVL         0x10
190#define ELCRS_INT11_LVL         0x08
191#define ELCRS_INT10_LVL         0x04
192#define ELCRS_INT9_LVL          0x02
193#define ELCRS_INT8_LVL          0x01
194#define ELCRM_INT7_LVL          0x80
195#define ELCRM_INT5_LVL          0x20
196
197
198#define NONSPECIFIC_EOI 0x20
199
200extern void En_Ext_Interrupt(int level);
201extern void Dis_Ext_Interrupt(int level);
202
203#define IRQ_VECTOR_BASE 0xbffffff0
204
205/*
206 * i8042 addresses
207 */
208#define I8042_DATA      0x60
209#define I8042_CS        0x64
210
211/*
212 * ns16550 addresses
213 */
214#define NS16550_PORT_A  0x3f8
215#define NS16550_PORT_B  0x2f8
216
217/*
218 * z85c30 addresses
219 */
220#define Z85C30_CTRL_B   0x840
221#define Z85C30_DATA_B   0x841
222#define Z85C30_CTRL_A   0x842
223#define Z85C30_DATA_A   0x843
224
225/*
226 *  Z85C30 Definations for the 422 interface.
227 */
228#define Z85C30_CLOCK     14745600
229
230#define PCI_SYS_MEM_BASE        0x80000000
231#define PCI_MEM_BASE            0xc0000000
232#define PCI_IO_BASE             0x80000000
233
234#define EIEIO asm volatile("eieio")
235
236/*
237 * As ports are all little endian we will perform swaps here on 16 and 32
238 * bit transfers
239 */
240extern uint16_t   Swap16(uint16_t   usVal);
241extern uint32_t   Swap32(uint32_t   ulVal);
242
243#define outport_byte(port, val)                 \
244        EIEIO;                                  \
245        *(volatile uint8_t*)(PCI_IO_BASE+       \
246                                (unsigned long)(port))=(val)
247
248#define outport_16(port, val)                   \
249        EIEIO;                                  \
250        *(volatile uint16_t*)(PCI_IO_BASE+      \
251                                 (unsigned long)(port))=Swap16(val)
252
253#define outport_32(port, val)                   \
254        EIEIO;                                  \
255        *(volatile uint32_t*)(PCI_IO_BASE+      \
256                                 (unsigned long)(port))=Swap32(val)
257
258#define inport_byte(port, val)                          \
259        EIEIO;                                          \
260        (val)=*(volatile uint8_t*)(PCI_IO_BASE+ \
261                                      (unsigned long)(port))
262
263#define inport_16(port, val)                                    \
264        EIEIO;                                                  \
265        (val)=Swap16(*(volatile uint16_t*)(PCI_IO_BASE+ \
266                                              (unsigned long)(port)))
267
268#define inport_32(port, val)                                    \
269        EIEIO;                                                  \
270        (val)=Swap32(*(volatile uint32_t*)(PCI_IO_BASE+ \
271                                              (unsigned long)(port)))
272
273/*
274 *  System Planar Board Registers
275 */
276typedef volatile struct _PLANARREGISTERS{
277    uint8_t   Reserved0[0x803];     /* Offset 0x000 */
278    uint8_t   SimmId;               /* Offset 0x803 */
279    uint8_t   SimmPresent;          /* Offset 0x804 */
280    uint8_t   Reserved1[3];
281    uint8_t   HardfileLight;        /* Offset 0x808 */
282    uint8_t   Reserved2[3];
283    uint8_t   EquipmentPresent1;    /* Offset 0x80C */
284    uint8_t   Reserved3;
285    uint8_t   EquipmentPresent2;    /* Offset 0x80e */
286    uint8_t   Reserved4;
287    uint8_t   PasswordProtect1;     /* Offset 0x810 */
288    uint8_t   Reserved5;
289    uint8_t   PasswordProtect2;     /* Offset 0x812 */
290    uint8_t   Reserved6;
291    uint8_t   L2Flush;              /* Offset 0x814 */
292    uint8_t   Reserved7[3];
293    uint8_t   Keylock;              /* Offset 0x818 */
294    uint8_t   Reserved8[0x3c];
295    uint8_t   BoardRevision;            /* Offset 0x854 */
296    uint8_t   Reserved9[0xf];
297    uint8_t   BoardID;                          /* Offset 0x864 */
298    uint8_t   Reserved10;
299    uint8_t   MotherboardMemoryType; /* Offset 0x866 */
300    uint8_t   Reserved11;
301    uint8_t   MezzanineMemoryType;  /* Offset 0x868 */
302} PLANARREGISTERS, *PPLANARREGISTERS;
303
304extern unsigned char ucSystemType;
305extern unsigned char ucBoardRevMaj;
306extern unsigned char ucBoardRevMin;
307extern unsigned long ulMemorySize;
308extern unsigned long ulCpuBusClock;
309
310#define SYS_TYPE_PPC1   0
311#define SYS_TYPE_PPC2   1
312#define SYS_TYPE_PPC1a  2
313#define SYS_TYPE_PPC2a  3
314#define SYS_TYPE_PPC4   4
315
316/*
317 * PCI initialisation
318 */
319void InitializePCI(void);
320
321/*
322 * VME initiaisation
323 */
324void InitializeUniverse();
325
326/*
327 * RTC initialisation
328 */
329void InitializeRTC(void);
330
331/*
332 * NvRAM initialisation
333 */
334void InitializeNvRAM(void);
335
336/*
337 *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
338 *  driver.
339 */
340
341#define BSP_TIMER_AVG_OVERHEAD   4  /* It typically takes xx clicks        */
342                                    /*     to start/stop the timer.        */
343#define BSP_TIMER_LEAST_VALID    1  /* Don't trust a value lower than this */
344
345/*
346 *  Convert decrement value to tenths of microsecnds (used by
347 *  shared timer driver).
348 *
349 *    + There are 4 bus cycles per click
350 *    + We return value in 1/10 microsecond units.
351 *   Modified following equation to integer equation to remove
352 *   floating point math.
353 *   (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
354 */
355
356#define BSP_Convert_decrementer( _value ) \
357  (int) (((_value) * 4000) / (ulCpuBusClock/10000))
358
359/*
360 *  Define the time limits for RTEMS Test Suite test durations.
361 *  Long test and short test duration limits are provided.  These
362 *  values are in seconds and need to be converted to ticks for the
363 *  application.
364 *
365 */
366
367#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
368#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
369
370/*
371 *  Stuff for Time Test 27
372 */
373
374#define MUST_WAIT_FOR_INTERRUPT 1
375
376#define Install_tm27_vector( _handler ) \
377  set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 )
378
379#define Cause_tm27_intr()  \
380  do { \
381    uint32_t   _clicks = 8; \
382    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
383  } while (0)
384
385
386#define Clear_tm27_intr() \
387  do { \
388    uint32_t   _clicks = 0xffffffff; \
389    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
390  } while (0)
391
392#define Lower_tm27_intr() \
393  do { \
394    uint32_t   _msr = 0; \
395    _ISR_Set_level( 0 ); \
396    asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
397    _msr |=  0x8002; \
398    asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
399  } while (0)
400
401
402/* Constants */
403
404/*
405 *  Device Driver Table Entries
406 */
407 
408/*
409 * NOTE: Use the standard Console driver entry
410 */
411 
412/*
413 * NOTE: Use the standard Clock driver entry
414 */
415 
416/*
417 * How many libio files we want
418 */
419 
420#define BSP_LIBIO_MAX_FDS       20
421
422/* functions */
423
424void bsp_start( void );
425
426void bsp_cleanup( void );
427
428rtems_isr_entry set_vector(                    /* returns old vector */
429  rtems_isr_entry     handler,                  /* isr routine        */
430  rtems_vector_number vector,                   /* vector number      */
431  int                 type                      /* RTEMS or RAW intr  */
432);
433
434/*
435 * spurious.c
436 */
437rtems_isr bsp_stub_handler(
438   rtems_vector_number trap
439);
440rtems_isr bsp_spurious_handler(
441   rtems_vector_number trap
442);
443void bsp_spurious_initialize();
444
445/*
446 * genvec.c
447 */
448void set_EE_vector(
449  rtems_isr_entry     handler,                  /* isr routine        */
450  rtems_vector_number vector                    /* vector number      */
451);
452void initialize_external_exception_vector();
453
454/*
455 * console.c
456 */
457void DEBUG_puts( char *string );
458void DEBUG_puth( uint32_t   ulHexNum );
459
460void BSP_fatal_return( void );
461
462extern rtems_configuration_table BSP_Configuration;     /* owned by BSP */
463
464extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
465
466extern uint32_t            bsp_isr_level;
467
468#endif /* ASM */
469
470#ifdef __cplusplus
471}
472#endif
473
474#endif
475/* end of include file */
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