| 1 | /* bsp.h |
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| 2 | * |
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| 3 | * This include file contains all board IO definitions. |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1998 by Radstone Technology |
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| 6 | * |
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| 7 | * |
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| 8 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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| 9 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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| 10 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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| 11 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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| 12 | * |
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| 13 | * You are hereby granted permission to use, copy, modify, and distribute |
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| 14 | * this file, provided that this notice, plus the above copyright notice |
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| 15 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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| 16 | * no support for this code. |
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| 17 | * |
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| 18 | * COPYRIGHT (c) 1989-1997. |
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| 19 | * On-Line Applications Research Corporation (OAR). |
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| 20 | * Copyright assigned to U.S. Government, 1994. |
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| 21 | * |
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| 22 | * The license and distribution terms for this file may in |
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| 23 | * the file LICENSE in this distribution or at |
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| 24 | * http:www.OARcorp.com/rtems/license.html. |
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| 25 | * |
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| 26 | * $Id$ |
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| 27 | */ |
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| 28 | |
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| 29 | #ifndef __BSP_h |
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| 30 | #define __BSP_h |
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| 31 | |
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| 32 | #include <bspopts.h> |
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| 33 | |
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| 34 | #ifdef __cplusplus |
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| 35 | extern "C" { |
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| 36 | #endif |
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| 37 | |
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| 38 | /* |
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| 39 | * confdefs.h overrides for this BSP: |
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| 40 | * - termios serial ports (defaults to 1) |
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| 41 | * - Interrupt stack space is not minimum if defined. |
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| 42 | */ |
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| 43 | |
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| 44 | #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 |
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| 45 | #define CONFIGURE_INTERRUPT_STACK_MEMORY (32 * 1024) |
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| 46 | |
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| 47 | /* Define processor identification. */ |
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| 48 | |
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| 49 | #define MPC601 1 |
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| 50 | #define MPC603 3 |
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| 51 | #define MPC604 4 |
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| 52 | #define MPC603e 6 |
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| 53 | #define MPC603ev 7 |
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| 54 | #define MPC604e 9 |
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| 55 | |
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| 56 | #ifdef ASM |
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| 57 | /* Definition of where to store registers in alignment handler */ |
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| 58 | #define ALIGN_REGS 0x0140 |
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| 59 | |
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| 60 | /* BAT register definitions for the MPC603 and MPC604. */ |
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| 61 | /* Define bit fields for upper MPC603/4 BAT registers. */ |
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| 62 | |
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| 63 | #define BEPI_FIELD_60X 0xFFFE0000 |
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| 64 | #define VALID_SUPERVISOR 0x2 |
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| 65 | #define VALID_PROBLEM 0x1 |
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| 66 | #define KEY_USER_60X 0x1 |
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| 67 | #define BL_128K 0x0 |
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| 68 | #define BL_256K (0x1<2) |
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| 69 | #define BL_512K (0x3<2) |
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| 70 | #define BL_1M (0x7<2) |
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| 71 | #define BL_2M (0xF<2) |
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| 72 | #define BL_4M (0x1F<2) |
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| 73 | #define BL_8M (0x3F<2) |
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| 74 | #define BL_16M (0x7F<2) |
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| 75 | #define BL_32M (0xFF<2) |
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| 76 | #define BL_64M (0x1FF<2) |
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| 77 | #define BL_128M (0x3FF<2) |
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| 78 | #define BL_256M (0x7FF<2) |
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| 79 | |
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| 80 | |
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| 81 | /* Define bit fields for lower MPC603/4 BAT registers. */ |
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| 82 | |
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| 83 | #define BRPN_FIELD_60X 0xFFFE0000 |
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| 84 | |
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| 85 | /* Common defines for BAT registers. */ |
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| 86 | /* Depending on the processor, the following may be in the upper */ |
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| 87 | /* and lower BAT register. */ |
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| 88 | |
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| 89 | #define WRITE_THRU 0x40 |
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| 90 | #define WRITE_BK 0x0 |
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| 91 | #define COHERE_EN 0x10 |
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| 92 | #define COHERE_DIS 0x0 |
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| 93 | #define CACHE_DIS 0x20 |
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| 94 | #define CACHE_EN 0x0 |
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| 95 | #define GUARDED_EN 0x8 |
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| 96 | #define GUARDED_DIS 0x0 |
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| 97 | #define PP_00 0x0 |
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| 98 | #define PP_01 0x1 |
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| 99 | #define PP_10 0x2 |
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| 100 | #define PP_11 0x3 |
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| 101 | |
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| 102 | /* HID0 definitions for MPC603 and MPC604 */ |
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| 103 | #define HID0 0x3f0 /* HID0 Special Purpose Register # */ |
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| 104 | /* HID1 definitions for MPC603e and MPC604e */ |
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| 105 | #define HID1 0x3f1 /* HID1 Special Purpose Register # */ |
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| 106 | |
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| 107 | #define H0_603_ICFI 0x0800 /* HID0 I-Cache Flash Invalidate */ |
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| 108 | #define H0_603_DCI 0x0400 /* HID0 D-Cache Flash Invalidate */ |
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| 109 | |
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| 110 | #define H0_60X_ICE 0x8000 /* HID0 I-Cache Enable */ |
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| 111 | #define H0_60X_DCE 0x4000 /* HID0 D-Cache Enable */ |
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| 112 | |
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| 113 | #define H0_604_BHTE 0x0004 /* HID0 Branch History Table enable */ |
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| 114 | #define H0_604_SIED 0x0080 /* HID0 Serial Instruction Execution */ |
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| 115 | #define H0_604_ICIA 0x0800 /* HID0 I-Cache Invalidate All */ |
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| 116 | #define H0_604_DCIA 0x0400 /* HID0 D-Cache Invalidate All */ |
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| 117 | |
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| 118 | #define BAT0U 528 |
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| 119 | #define BAT0L 529 |
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| 120 | #define BAT1U 530 |
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| 121 | #define BAT1L 531 |
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| 122 | #define BAT2U 532 |
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| 123 | #define BAT2L 533 |
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| 124 | #define BAT3U 534 |
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| 125 | #define BAT3L 535 |
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| 126 | #define SPRG0 272 |
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| 127 | #define SPRG1 273 |
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| 128 | |
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| 129 | /* MSR bit settings */ |
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| 130 | #define MSR_LE 0x0001 |
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| 131 | #define MSR_RI 0x0002 |
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| 132 | #define MSR_DR 0x0010 |
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| 133 | #define MSR_IR 0x0020 |
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| 134 | #define MSR_IP 0x0040 |
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| 135 | #define MSR_FE1 0x0100 |
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| 136 | #define MSR_BE 0x0200 |
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| 137 | #define MSR_SE 0x0400 |
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| 138 | #define MSR_FE0 0x0800 |
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| 139 | #define MSR_ME 0x1000 |
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| 140 | #define MSR_FP 0x2000 |
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| 141 | #define MSR_PR 0x4000 |
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| 142 | #define MSR_EE 0x8000 |
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| 143 | #define MSR_ILE 0x0001 /* Upper 16 bits */ |
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| 144 | #define MSR_POW 0x0004 /* Upper 16 bits */ |
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| 145 | #else |
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| 146 | #include <rtems.h> |
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| 147 | #include <console.h> |
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| 148 | #include <clockdrv.h> |
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| 149 | #include <iosupp.h> |
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| 150 | #include <tod.h> |
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| 151 | #include <nvram.h> |
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| 152 | |
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| 153 | /* |
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| 154 | * PPCn_60x Interupt Definations. |
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| 155 | */ |
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| 156 | #define PPCN_60X_8259_IRQ_BASE ( PPC_IRQ_LAST + 1 ) |
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| 157 | |
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| 158 | /* |
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| 159 | * 8259 IRQ definations. |
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| 160 | */ |
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| 161 | #define PPCN_60X_IRQ_SYS_TIMER (PPCN_60X_8259_IRQ_BASE + 0) |
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| 162 | #define PPCN_60X_IRQ_KBD (PPCN_60X_8259_IRQ_BASE + 1) |
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| 163 | #define PPCN_60X_IRQ_COM2 (PPCN_60X_8259_IRQ_BASE + 3) |
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| 164 | #define PPCN_60X_IRQ_COM1 (PPCN_60X_8259_IRQ_BASE + 4) |
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| 165 | #define PPCN_60X_IRQ_CIO (PPCN_60X_8259_IRQ_BASE + 5) |
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| 166 | #define PPCN_60X_IRQ_FDC (PPCN_60X_8259_IRQ_BASE + 6) |
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| 167 | #define PPCN_60X_IRQ_LPT (PPCN_60X_8259_IRQ_BASE + 7) |
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| 168 | #define PPCN_60X_IRQ_RTC (PPCN_60X_8259_IRQ_BASE + 8) |
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| 169 | #define PPCN_60X_IRQ_COM3_4 (PPCN_60X_8259_IRQ_BASE + 10) |
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| 170 | #define PPCN_60X_IRQ_MSE (PPCN_60X_8259_IRQ_BASE + 12) |
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| 171 | #define PPCN_60X_IRQ_SCSI (PPCN_60X_8259_IRQ_BASE + 13) |
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| 172 | |
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| 173 | /* |
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| 174 | * PCI interrupts as read from line register map directly to |
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| 175 | * ISA interrupt lines 9, 11, 14 and 15. |
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| 176 | */ |
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| 177 | #define PPCN_60X_IRQ_PCI(n) (PPCN_60X_8259_IRQ_BASE + (n)) |
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| 178 | |
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| 179 | #define MAX_BOARD_IRQS (PPCN_60X_8259_IRQ_BASE + 15) |
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| 180 | |
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| 181 | #define ISA8259_M_CTRL 0x20 |
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| 182 | #define ISA8259_S_CTRL 0xa0 |
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| 183 | #define ISA8259_M_MASK 0x21 |
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| 184 | #define ISA8259_S_MASK 0xa1 |
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| 185 | #define ISA8259_M_ELCR 0x4d0 |
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| 186 | #define ISA8259_S_ELCR 0x4d1 |
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| 187 | |
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| 188 | #define ELCRS_INT15_LVL 0x80 |
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| 189 | #define ELCRS_INT14_LVL 0x40 |
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| 190 | #define ELCRS_INT12_LVL 0x10 |
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| 191 | #define ELCRS_INT11_LVL 0x08 |
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| 192 | #define ELCRS_INT10_LVL 0x04 |
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| 193 | #define ELCRS_INT9_LVL 0x02 |
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| 194 | #define ELCRS_INT8_LVL 0x01 |
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| 195 | #define ELCRM_INT7_LVL 0x80 |
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| 196 | #define ELCRM_INT5_LVL 0x20 |
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| 197 | |
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| 198 | |
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| 199 | #define NONSPECIFIC_EOI 0x20 |
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| 200 | |
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| 201 | extern void En_Ext_Interrupt(int level); |
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| 202 | extern void Dis_Ext_Interrupt(int level); |
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| 203 | |
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| 204 | #define IRQ_VECTOR_BASE 0xbffffff0 |
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| 205 | |
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| 206 | /* |
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| 207 | * i8042 addresses |
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| 208 | */ |
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| 209 | #define I8042_DATA 0x60 |
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| 210 | #define I8042_CS 0x64 |
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| 211 | |
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| 212 | /* |
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| 213 | * ns16550 addresses |
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| 214 | */ |
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| 215 | #define NS16550_PORT_A 0x3f8 |
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| 216 | #define NS16550_PORT_B 0x2f8 |
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| 217 | |
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| 218 | /* |
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| 219 | * z85c30 addresses |
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| 220 | */ |
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| 221 | #define Z85C30_CTRL_B 0x840 |
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| 222 | #define Z85C30_DATA_B 0x841 |
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| 223 | #define Z85C30_CTRL_A 0x842 |
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| 224 | #define Z85C30_DATA_A 0x843 |
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| 225 | |
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| 226 | /* |
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| 227 | * Z85C30 Definations for the 422 interface. |
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| 228 | */ |
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| 229 | #define Z85C30_CLOCK 14745600 |
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| 230 | |
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| 231 | #define PCI_SYS_MEM_BASE 0x80000000 |
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| 232 | #define PCI_MEM_BASE 0xc0000000 |
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| 233 | #define PCI_IO_BASE 0x80000000 |
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| 234 | |
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| 235 | #define EIEIO asm volatile("eieio") |
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| 236 | |
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| 237 | /* |
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| 238 | * As ports are all little endian we will perform swaps here on 16 and 32 |
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| 239 | * bit transfers |
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| 240 | */ |
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| 241 | extern unsigned16 Swap16(unsigned16 usVal); |
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| 242 | extern unsigned32 Swap32(unsigned32 ulVal); |
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| 243 | |
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| 244 | #define outport_byte(port, val) \ |
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| 245 | EIEIO; \ |
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| 246 | *(volatile unsigned8 *)(PCI_IO_BASE+ \ |
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| 247 | (unsigned long)(port))=(val) |
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| 248 | |
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| 249 | #define outport_16(port, val) \ |
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| 250 | EIEIO; \ |
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| 251 | *(volatile unsigned16 *)(PCI_IO_BASE+ \ |
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| 252 | (unsigned long)(port))=Swap16(val) |
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| 253 | |
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| 254 | #define outport_32(port, val) \ |
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| 255 | EIEIO; \ |
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| 256 | *(volatile unsigned32 *)(PCI_IO_BASE+ \ |
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| 257 | (unsigned long)(port))=Swap32(val) |
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| 258 | |
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| 259 | #define inport_byte(port, val) \ |
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| 260 | EIEIO; \ |
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| 261 | (val)=*(volatile unsigned8 *)(PCI_IO_BASE+ \ |
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| 262 | (unsigned long)(port)) |
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| 263 | |
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| 264 | #define inport_16(port, val) \ |
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| 265 | EIEIO; \ |
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| 266 | (val)=Swap16(*(volatile unsigned16 *)(PCI_IO_BASE+ \ |
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| 267 | (unsigned long)(port))) |
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| 268 | |
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| 269 | #define inport_32(port, val) \ |
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| 270 | EIEIO; \ |
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| 271 | (val)=Swap32(*(volatile unsigned32 *)(PCI_IO_BASE+ \ |
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| 272 | (unsigned long)(port))) |
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| 273 | |
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| 274 | /* |
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| 275 | * System Planar Board Registers |
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| 276 | */ |
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| 277 | typedef volatile struct _PLANARREGISTERS{ |
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| 278 | unsigned8 Reserved0[0x803]; /* Offset 0x000 */ |
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| 279 | unsigned8 SimmId; /* Offset 0x803 */ |
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| 280 | unsigned8 SimmPresent; /* Offset 0x804 */ |
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| 281 | unsigned8 Reserved1[3]; |
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| 282 | unsigned8 HardfileLight; /* Offset 0x808 */ |
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| 283 | unsigned8 Reserved2[3]; |
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| 284 | unsigned8 EquipmentPresent1; /* Offset 0x80C */ |
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| 285 | unsigned8 Reserved3; |
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| 286 | unsigned8 EquipmentPresent2; /* Offset 0x80e */ |
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| 287 | unsigned8 Reserved4; |
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| 288 | unsigned8 PasswordProtect1; /* Offset 0x810 */ |
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| 289 | unsigned8 Reserved5; |
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| 290 | unsigned8 PasswordProtect2; /* Offset 0x812 */ |
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| 291 | unsigned8 Reserved6; |
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| 292 | unsigned8 L2Flush; /* Offset 0x814 */ |
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| 293 | unsigned8 Reserved7[3]; |
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| 294 | unsigned8 Keylock; /* Offset 0x818 */ |
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| 295 | unsigned8 Reserved8[0x3c]; |
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| 296 | unsigned8 BoardRevision; /* Offset 0x854 */ |
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| 297 | unsigned8 Reserved9[0xf]; |
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| 298 | unsigned8 BoardID; /* Offset 0x864 */ |
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| 299 | unsigned8 Reserved10; |
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| 300 | unsigned8 MotherboardMemoryType; /* Offset 0x866 */ |
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| 301 | unsigned8 Reserved11; |
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| 302 | unsigned8 MezzanineMemoryType; /* Offset 0x868 */ |
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| 303 | } PLANARREGISTERS, *PPLANARREGISTERS; |
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| 304 | |
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| 305 | extern unsigned char ucSystemType; |
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| 306 | extern unsigned char ucBoardRevMaj; |
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| 307 | extern unsigned char ucBoardRevMin; |
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| 308 | extern unsigned long ulMemorySize; |
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| 309 | extern unsigned long ulCpuBusClock; |
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| 310 | |
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| 311 | #define SYS_TYPE_PPC1 0 |
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| 312 | #define SYS_TYPE_PPC2 1 |
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| 313 | #define SYS_TYPE_PPC1a 2 |
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| 314 | #define SYS_TYPE_PPC2a 3 |
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| 315 | #define SYS_TYPE_PPC4 4 |
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| 316 | |
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| 317 | /* |
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| 318 | * PCI initialisation |
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| 319 | */ |
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| 320 | void InitializePCI(void); |
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| 321 | |
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| 322 | /* |
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| 323 | * VME initiaisation |
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| 324 | */ |
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| 325 | void InitializeUniverse(); |
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| 326 | |
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| 327 | /* |
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| 328 | * RTC initialisation |
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| 329 | */ |
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| 330 | void InitializeRTC(void); |
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| 331 | |
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| 332 | /* |
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| 333 | * NvRAM initialisation |
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| 334 | */ |
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| 335 | void InitializeNvRAM(void); |
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| 336 | |
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| 337 | /* |
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| 338 | * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer |
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| 339 | * driver. |
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| 340 | */ |
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| 341 | |
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| 342 | #define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */ |
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| 343 | /* to start/stop the timer. */ |
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| 344 | #define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ |
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| 345 | |
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| 346 | /* |
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| 347 | * Convert decrement value to tenths of microsecnds (used by |
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| 348 | * shared timer driver). |
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| 349 | * |
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| 350 | * + There are 4 bus cycles per click |
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| 351 | * + We return value in 1/10 microsecond units. |
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| 352 | * Modified following equation to integer equation to remove |
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| 353 | * floating point math. |
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| 354 | * (int) ((float)(_value) / ((66.67 * 0.1) / 4.0)) |
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| 355 | */ |
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| 356 | |
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| 357 | #define BSP_Convert_decrementer( _value ) \ |
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| 358 | (int) (((_value) * 4000) / (ulCpuBusClock/10000)) |
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| 359 | |
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| 360 | /* |
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| 361 | * Define the time limits for RTEMS Test Suite test durations. |
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| 362 | * Long test and short test duration limits are provided. These |
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| 363 | * values are in seconds and need to be converted to ticks for the |
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| 364 | * application. |
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| 365 | * |
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| 366 | */ |
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| 367 | |
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| 368 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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| 369 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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| 370 | |
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| 371 | /* |
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| 372 | * Stuff for Time Test 27 |
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| 373 | */ |
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| 374 | |
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| 375 | #define MUST_WAIT_FOR_INTERRUPT 1 |
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| 376 | |
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| 377 | #define Install_tm27_vector( _handler ) \ |
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| 378 | set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 ) |
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| 379 | |
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| 380 | #define Cause_tm27_intr() \ |
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| 381 | do { \ |
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| 382 | unsigned32 _clicks = 8; \ |
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| 383 | asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ |
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| 384 | } while (0) |
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| 385 | |
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| 386 | |
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| 387 | #define Clear_tm27_intr() \ |
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| 388 | do { \ |
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| 389 | unsigned32 _clicks = 0xffffffff; \ |
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| 390 | asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ |
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| 391 | } while (0) |
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| 392 | |
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| 393 | #define Lower_tm27_intr() \ |
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| 394 | do { \ |
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| 395 | unsigned32 _msr = 0; \ |
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| 396 | _ISR_Set_level( 0 ); \ |
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| 397 | asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ |
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| 398 | _msr |= 0x8002; \ |
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| 399 | asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ |
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| 400 | } while (0) |
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| 401 | |
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| 402 | |
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| 403 | /* Constants */ |
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| 404 | |
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| 405 | /* |
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| 406 | * Device Driver Table Entries |
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| 407 | */ |
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| 408 | |
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| 409 | /* |
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| 410 | * NOTE: Use the standard Console driver entry |
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| 411 | */ |
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| 412 | |
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| 413 | /* |
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| 414 | * NOTE: Use the standard Clock driver entry |
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| 415 | */ |
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| 416 | |
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| 417 | /* |
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| 418 | * How many libio files we want |
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| 419 | */ |
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| 420 | |
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| 421 | #define BSP_LIBIO_MAX_FDS 20 |
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| 422 | |
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| 423 | /* functions */ |
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| 424 | |
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| 425 | void bsp_start( void ); |
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| 426 | |
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| 427 | void bsp_cleanup( void ); |
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| 428 | |
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| 429 | rtems_isr_entry set_vector( /* returns old vector */ |
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| 430 | rtems_isr_entry handler, /* isr routine */ |
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| 431 | rtems_vector_number vector, /* vector number */ |
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| 432 | int type /* RTEMS or RAW intr */ |
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| 433 | ); |
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| 434 | |
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| 435 | /* |
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| 436 | * spurious.c |
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| 437 | */ |
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| 438 | rtems_isr bsp_stub_handler( |
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| 439 | rtems_vector_number trap |
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| 440 | ); |
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| 441 | rtems_isr bsp_spurious_handler( |
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| 442 | rtems_vector_number trap |
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| 443 | ); |
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| 444 | void bsp_spurious_initialize(); |
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| 445 | |
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| 446 | /* |
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| 447 | * genvec.c |
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| 448 | */ |
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| 449 | void set_EE_vector( |
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| 450 | rtems_isr_entry handler, /* isr routine */ |
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| 451 | rtems_vector_number vector /* vector number */ |
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| 452 | ); |
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| 453 | void initialize_external_exception_vector(); |
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| 454 | |
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| 455 | /* |
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| 456 | * console.c |
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| 457 | */ |
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| 458 | void DEBUG_puts( char *string ); |
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| 459 | void DEBUG_puth( unsigned32 ulHexNum ); |
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| 460 | |
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| 461 | void BSP_fatal_return( void ); |
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| 462 | |
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| 463 | extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ |
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| 464 | |
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| 465 | extern rtems_cpu_table Cpu_table; /* owned by BSP */ |
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| 466 | |
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| 467 | extern unsigned32 bsp_isr_level; |
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| 468 | |
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| 469 | #endif /* ASM */ |
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| 470 | |
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| 471 | #ifdef __cplusplus |
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| 472 | } |
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| 473 | #endif |
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| 474 | |
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| 475 | #endif |
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| 476 | /* end of include file */ |
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