1 | /* |
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2 | * This file contains the TTY driver table for the PPCn_60x |
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3 | * |
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4 | * COPYRIGHT (c) 1998 by Radstone Technology |
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5 | * |
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6 | * |
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7 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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8 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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9 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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10 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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11 | * |
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12 | * You are hereby granted permission to use, copy, modify, and distribute |
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13 | * this file, provided that this notice, plus the above copyright notice |
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14 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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15 | * no support for this code. |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #include "i8042vga.h" |
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21 | #include "ns16550.h" |
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22 | #include "z85c30.h" |
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23 | |
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24 | #include <pci.h> |
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25 | |
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26 | #define PMX1553_BUS 2 |
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27 | #define PMX1553_SLOT 1 |
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28 | |
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29 | /* |
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30 | * Configuration specific probe routines |
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31 | */ |
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32 | static boolean config_PMX1553_probe(int minor); |
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33 | static boolean config_z85c30_probe(int minor); |
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34 | |
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35 | /* |
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36 | * The following table configures the console drivers used in this BSP. |
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37 | * |
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38 | * The first entry which, when probed, is available, will be named /dev/console, |
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39 | * all others being given the name indicated. |
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40 | * |
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41 | * Each field is interpreted thus: |
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42 | * |
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43 | * sDeviceName This is the name of the device. |
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44 | * pDeviceFns This is a pointer to the set of driver routines to use. |
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45 | * pDeviceFlow This is a pointer to the set of flow control routines to |
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46 | * use. Serial device drivers will typically supply RTSCTS |
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47 | * and DTRCTS handshake routines for DCE to DCE communication, |
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48 | * however for DCE to DTE communication, no such routines |
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49 | * should be necessary as RTS will be driven automatically |
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50 | * when the transmitter is active. |
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51 | * ulMargin The high water mark in the input buffer is set to the buffer |
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52 | * size less ulMargin. Once this level is reached, the driver's |
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53 | * flow control routine used to stop the remote transmitter will |
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54 | * be called. This figure should be greater than or equal to |
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55 | * the number of stages of FIFO between the transmitter and |
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56 | * receiver. |
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57 | * ulHysteresis After the high water mark specified by ulMargin has been |
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58 | * reached, the driver's routine to re-start the remote |
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59 | * transmitter will be called once the level in the input |
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60 | * buffer has fallen by ulHysteresis bytes. |
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61 | * pDeviceParams This contains either device specific data or a pointer to a |
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62 | * device specific structure containing additional information |
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63 | * not provided in this table. |
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64 | * ulCtrlPort1 This is the primary control port number for the device. This |
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65 | * may be used to specify different instances of the same device |
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66 | * type. |
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67 | * ulCtrlPort2 This is the secondary control port number, of use when a given |
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68 | * device has more than one available channel. |
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69 | * ulDataPort This is the port number for the data port of the device |
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70 | * ulIntVector This encodes the interrupt vector of the device. |
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71 | * |
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72 | */ |
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73 | console_tbl Console_Port_Tbl[] = { |
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74 | { |
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75 | "/dev/vga", /* sDeviceName */ |
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76 | &i8042vga_fns, /* pDeviceFns */ |
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77 | NULL, /* deviceProbe */ |
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78 | NULL, /* pDeviceFlow */ |
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79 | 0, /* ulMargin */ |
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80 | 0, /* ulHysteresis */ |
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81 | (void *)0, /* pDeviceParams */ |
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82 | I8042_CS, /* ulCtrlPort1 */ |
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83 | 0, /* ulCtrlPort2 */ |
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84 | I8042_DATA, /* ulDataPort */ |
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85 | PPCN_60X_IRQ_KBD /* ulIntVector */ |
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86 | }, |
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87 | { |
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88 | "/dev/com1", /* sDeviceName */ |
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89 | &ns16550_fns, /* pDeviceFns */ |
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90 | NULL, /* deviceProbe */ |
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91 | &ns16550_flow_RTSCTS, /* pDeviceFlow */ |
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92 | 16, /* ulMargin */ |
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93 | 8, /* ulHysteresis */ |
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94 | (void *)9600, /* baud rate */ /* pDeviceParams */ |
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95 | NS16550_PORT_A, /* ulCtrlPort1 */ |
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96 | 0, /* ulCtrlPort2 */ |
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97 | NS16550_PORT_A, /* ulDataPort */ |
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98 | PPCN_60X_IRQ_COM1 /* ulIntVector */ |
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99 | }, |
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100 | { |
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101 | "/dev/ser1", /* sDeviceName */ |
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102 | &ns16550_fns, /* pDeviceFns */ |
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103 | config_PMX1553_probe, /* deviceProbe */ |
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104 | &ns16550_flow_RTSCTS, /* pDeviceFlow */ |
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105 | 80, /* ulMargin */ |
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106 | 8, /* ulHysteresis */ |
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107 | (void *)9600, /* baud rate */ /* pDeviceParams */ |
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108 | PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */ |
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109 | PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */ |
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110 | 1, /* Channel 1-4 */ /* ulDataPort */ |
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111 | 0 /* RS232 */ /* ulIntVector */ |
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112 | }, |
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113 | { |
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114 | "/dev/ser2", /* sDeviceName */ |
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115 | &ns16550_fns, /* pDeviceFns */ |
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116 | config_PMX1553_probe, /* deviceProbe */ |
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117 | &ns16550_flow_RTSCTS, /* pDeviceFlow */ |
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118 | 80, /* ulMargin */ |
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119 | 8, /* ulHysteresis */ |
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120 | (void *)9600, /* baud rate */ /* pDeviceParams */ |
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121 | PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */ |
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122 | PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */ |
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123 | 2, /* Channel 1-4 */ /* ulDataPort */ |
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124 | 0 /* RS232 */ /* ulIntVector */ |
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125 | }, |
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126 | { |
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127 | "/dev/ser3", /* sDeviceName */ |
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128 | &ns16550_fns, /* pDeviceFns */ |
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129 | config_PMX1553_probe, /* deviceProbe */ |
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130 | &ns16550_flow_RTSCTS, /* pDeviceFlow */ |
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131 | 96, /* ulMargin */ |
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132 | 8, /* ulHysteresis */ |
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133 | (void *)57600, /* baud rate */ /* pDeviceParams */ |
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134 | PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */ |
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135 | PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */ |
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136 | 3, /* Channel 1-4 */ /* ulDataPort */ |
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137 | 0 /* RS232 */ /* ulIntVector */ |
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138 | }, |
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139 | { |
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140 | "/dev/ser4", /* sDeviceName */ |
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141 | &ns16550_fns, /* pDeviceFns */ |
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142 | config_PMX1553_probe, /* deviceProbe */ |
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143 | &ns16550_flow_RTSCTS, /* pDeviceFlow */ |
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144 | 96, /* ulMargin */ |
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145 | 8, /* ulHysteresis */ |
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146 | (void *)57600, /* baud rate */ /* pDeviceParams */ |
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147 | PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */ |
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148 | PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */ |
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149 | 4, /* Channel 1-4 */ /* ulDataPort */ |
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150 | 0 /* RS232 */ /* ulIntVector */ |
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151 | }, |
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152 | #if !PPCN_60X_USE_DINK |
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153 | { |
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154 | "/dev/com2", /* sDeviceName */ |
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155 | &ns16550_fns, /* pDeviceFns */ |
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156 | NULL, /* deviceProbe */ |
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157 | &ns16550_flow_RTSCTS, /* pDeviceFlow */ |
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158 | 16, /* ulMargin */ |
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159 | 8, /* ulHysteresis */ |
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160 | (void *)9600, /* baud rate */ /* pDeviceParams */ |
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161 | NS16550_PORT_B, /* ulCtrlPort1 */ |
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162 | 0, /* ulCtrlPort2 */ |
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163 | NS16550_PORT_B, /* ulDataPort */ |
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164 | PPCN_60X_IRQ_COM2 /* ulIntVector */ |
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165 | }, |
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166 | #endif |
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167 | { |
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168 | "/dev/com3", /* sDeviceName */ |
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169 | &z85c30_fns, /* pDeviceFns */ |
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170 | config_z85c30_probe, /* deviceProbe */ |
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171 | &z85c30_flow_RTSCTS, /* pDeviceFlow */ |
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172 | 16, /* ulMargin */ |
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173 | 8, /* ulHysteresis */ |
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174 | (void *)9600, /* baud rate */ /* pDeviceParams */ |
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175 | Z85C30_CTRL_A, /* ulCtrlPort1 */ |
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176 | Z85C30_CTRL_A, /* ulCtrlPort2 */ |
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177 | Z85C30_DATA_A, /* ulDataPort */ |
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178 | PPCN_60X_IRQ_COM3_4 /* ulIntVector */ |
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179 | }, |
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180 | { |
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181 | "/dev/com4", /* sDeviceName */ |
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182 | &z85c30_fns, /* pDeviceFns */ |
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183 | config_z85c30_probe, /* deviceProbe */ |
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184 | &z85c30_flow_RTSCTS, /* pDeviceFlow */ |
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185 | 16, /* ulMargin */ |
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186 | 8, /* ulHysteresis */ |
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187 | (void *)9600, /* baud rate */ /* pDeviceParams */ |
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188 | Z85C30_CTRL_B, /* ulCtrlPort1 */ |
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189 | Z85C30_CTRL_A, /* ulCtrlPort2 */ |
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190 | Z85C30_DATA_B, /* ulDataPort */ |
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191 | PPCN_60X_IRQ_COM3_4 /* ulIntVector */ |
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192 | } |
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193 | }; |
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194 | |
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195 | /* |
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196 | * Define serial port write registers structure. |
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197 | */ |
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198 | typedef volatile struct _SP_WRITE_REGISTERS { |
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199 | unsigned char TransmitBuffer; |
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200 | unsigned char InterruptEnable; |
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201 | unsigned char FifoControl; |
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202 | unsigned char LineControl; |
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203 | unsigned char ModemControl; |
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204 | unsigned char Reserved1; |
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205 | unsigned char ModemStatus; |
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206 | unsigned char ScratchPad; |
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207 | } SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS; |
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208 | |
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209 | static boolean config_PMX1553_probe(int minor) |
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210 | { |
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211 | unsigned8 ucBusNumber, ucSlotNumber, ucChannel; |
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212 | unsigned8 ucIntLine; |
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213 | unsigned32 ulPortBase, ulMemBase, ulDeviceID; |
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214 | unsigned8 *pucSIO_cir, *pucUart_int_sr, *pucUartDevIntReg; |
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215 | PSP_WRITE_REGISTERS pNS16550Write; |
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216 | |
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217 | /* |
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218 | * Extract PCI bus/slot and channel number |
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219 | */ |
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220 | ucBusNumber=Console_Port_Tbl[minor].ulCtrlPort1; |
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221 | ucSlotNumber=Console_Port_Tbl[minor].ulCtrlPort2; |
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222 | ucChannel=Console_Port_Tbl[minor].ulDataPort; |
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223 | |
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224 | PCIConfigRead32(ucBusNumber, |
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225 | ucSlotNumber, |
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226 | 0, |
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227 | PCI_CONFIG_VENDOR_LOW, |
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228 | &ulDeviceID); |
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229 | |
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230 | if(ulDeviceID!=0x000111b5) |
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231 | { |
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232 | return FALSE; |
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233 | } |
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234 | |
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235 | /* |
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236 | * At this point we know we have a PMC1553 or PMX1553 card |
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237 | * |
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238 | * Check for PMX1553 uart legacy IO ports |
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239 | */ |
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240 | PCIConfigRead32(ucBusNumber, |
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241 | ucSlotNumber, |
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242 | 0, |
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243 | PCI_CONFIG_BAR_3, |
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244 | &ulPortBase); |
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245 | |
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246 | if(ulPortBase==0) |
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247 | { |
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248 | /* |
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249 | * This is either a PMC1553 or we can't see the uart |
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250 | * registers |
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251 | */ |
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252 | return FALSE; |
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253 | } |
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254 | |
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255 | PCIConfigRead32(ucBusNumber, |
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256 | ucSlotNumber, |
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257 | 0, |
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258 | PCI_CONFIG_BAR_2, |
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259 | &ulMemBase); |
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260 | |
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261 | pucUartDevIntReg=(unsigned8 *)(PCI_MEM_BASE+ulMemBase); |
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262 | pucUart_int_sr=(unsigned8 *)(PCI_MEM_BASE+ulMemBase+0x10); |
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263 | pucSIO_cir=(unsigned8 *)(PCI_MEM_BASE+ulMemBase+0x18); |
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264 | |
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265 | /* |
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266 | * Use ulIntVector field to select RS232/RS422 |
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267 | */ |
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268 | if(Console_Port_Tbl[minor].ulIntVector==0) |
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269 | { |
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270 | /* |
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271 | * Select RS232 mode |
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272 | */ |
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273 | *pucSIO_cir&=~(1<<(ucChannel-1)); |
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274 | } |
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275 | else |
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276 | { |
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277 | /* |
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278 | * Select RS422 mode |
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279 | */ |
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280 | *pucSIO_cir|=1<<(ucChannel-1); |
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281 | } |
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282 | EIEIO; |
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283 | /* |
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284 | * Bring device out of reset |
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285 | */ |
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286 | *pucSIO_cir&=0xbf; |
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287 | EIEIO; |
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288 | /* |
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289 | * Enable all channels as active |
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290 | */ |
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291 | *pucSIO_cir|=0x10; |
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292 | EIEIO; |
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293 | *pucSIO_cir&=0xdf; |
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294 | |
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295 | PCIConfigRead8(ucBusNumber, |
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296 | ucSlotNumber, |
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297 | 0, |
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298 | PCI_CONFIG_INTERRUPTLINE, |
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299 | &ucIntLine); |
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300 | |
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301 | ulPortBase&=~PCI_ADDRESS_IO_SPACE; |
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302 | |
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303 | ulPortBase+=8*(ucChannel-1); |
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304 | |
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305 | Console_Port_Tbl[minor].ulCtrlPort1= |
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306 | Console_Port_Tbl[minor].ulDataPort=ulPortBase; |
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307 | if(Console_Port_Tbl[minor].pDeviceFns!=&ns16550_fns_polled) |
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308 | { |
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309 | Console_Port_Tbl[minor].ulIntVector=PPCN_60X_IRQ_PCI(ucIntLine); |
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310 | |
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311 | /* |
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312 | * Enable interrupt |
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313 | */ |
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314 | *pucUart_int_sr=(~*pucUart_int_sr)&(0x08<<ucChannel); |
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315 | |
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316 | /* |
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317 | * Enable interrupt to PCI |
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318 | */ |
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319 | *pucUartDevIntReg=(~*pucUartDevIntReg)&0x80; |
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320 | } |
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321 | else |
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322 | { |
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323 | /* |
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324 | * Disable interrupt |
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325 | */ |
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326 | *pucUart_int_sr&=(0x08<<ucChannel); |
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327 | } |
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328 | |
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329 | /* |
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330 | * Enable Auto CTS to facilitate flow control |
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331 | */ |
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332 | pNS16550Write=(PSP_WRITE_REGISTERS)Console_Port_Tbl[minor].ulCtrlPort1; |
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333 | /* |
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334 | * Enable special register set and unlock Enhanced Feature Register |
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335 | */ |
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336 | outport_byte(&pNS16550Write->LineControl, 0xbf); |
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337 | /* |
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338 | * Unlock enhanced function bits |
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339 | */ |
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340 | outport_byte(&pNS16550Write->FifoControl, 0x10); |
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341 | /* |
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342 | * Disable special register set and lock Enhanced Feature Register |
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343 | */ |
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344 | outport_byte(&pNS16550Write->LineControl, 0); |
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345 | /* |
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346 | * Select div 1 |
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347 | */ |
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348 | outport_byte(&pNS16550Write->ModemControl, 0x00); |
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349 | /* |
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350 | * Enable special register set and unlock Enhanced Feature Register |
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351 | */ |
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352 | outport_byte(&pNS16550Write->LineControl, 0xbf); |
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353 | /* |
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354 | * Lock enhanced function bits and enable auto CTS |
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355 | */ |
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356 | outport_byte(&pNS16550Write->FifoControl, 0x80); |
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357 | /* |
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358 | * Disable special register set and lock Enhanced Feature Register |
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359 | */ |
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360 | outport_byte(&pNS16550Write->LineControl, 0); |
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361 | |
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362 | /* |
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363 | * The PMX1553 currently uses a 16 MHz clock rather than the |
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364 | * 7.3728 MHz clock described in the ST16C654 data sheet. When |
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365 | * available, 22.1184 MHz will be used allowing rates up to |
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366 | * 1382400 baud (RS422 only). |
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367 | */ |
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368 | #if 1 |
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369 | /* |
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370 | * Scale requested baud rate for 16 MHz clock |
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371 | */ |
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372 | (unsigned32)Console_Port_Tbl[minor].pDeviceParams*=7373; |
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373 | (unsigned32)Console_Port_Tbl[minor].pDeviceParams/=16000; |
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374 | #else |
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375 | /* |
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376 | * Scale requested baud rate for 22.1184 MHz clock |
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377 | */ |
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378 | (unsigned32)Console_Port_Tbl[minor].pDeviceParams/=3; |
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379 | #endif |
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380 | /* |
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381 | * In order to maintain maximum data rate accuracy, we will |
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382 | * apply a div 4 here rather than in hardware (using MCR bit 7). |
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383 | */ |
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384 | (unsigned32)Console_Port_Tbl[minor].pDeviceParams/=4; |
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385 | |
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386 | return(TRUE); |
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387 | } |
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388 | |
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389 | static boolean config_z85c30_probe(int minor) |
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390 | { |
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391 | /* |
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392 | * PPC1 and PPC1a do not have this device |
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393 | */ |
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394 | if((ucSystemType==SYS_TYPE_PPC1) || |
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395 | (ucSystemType==SYS_TYPE_PPC1a)) |
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396 | { |
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397 | return (FALSE); |
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398 | } |
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399 | |
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400 | /* |
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401 | * All other boards supported by this BSP have the z85c30 device |
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402 | */ |
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403 | |
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404 | /* |
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405 | * Ensure that CIO port B is configured for |
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406 | * default driver enable |
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407 | */ |
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408 | outport_byte(0x861, 0x33); |
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409 | |
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410 | return(TRUE); |
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411 | } |
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412 | |
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