1 | #ifndef RTEMS_BSP_VME_CONFIG_H |
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2 | #define RTEMS_BSP_VME_CONFIG_H |
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3 | /* VMEConfig.h, S. Kate Feng modified it for MVME5500 3/04 |
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4 | * |
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5 | * May 2011 : Use the VME shared IRQ handlers. |
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6 | * |
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7 | * It seems that the implementation of VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND |
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8 | * is not fully developed. The UNIV_REGOFF_VCSR_BS is defined for VME64 |
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9 | * specification, which does not apply to a VME32 crate. In order to avoid |
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10 | * spurious VME interrupts, a better and more universal solution is |
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11 | * to flush the vmeUniverse FIFO by reading a register back within the |
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12 | * users' Interrupt Service Routine (ISR) before returning. |
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13 | * |
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14 | * Some devices might require the ISR to issue an interrupt status READ |
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15 | * after its IRQ is cleared, but before its corresponding interrupt |
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16 | * is enabled again. |
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17 | * |
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18 | */ |
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19 | /* BSP specific address space configuration parameters */ |
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20 | |
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21 | /* |
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22 | * The BSP maps VME address ranges into |
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23 | * one BAT. |
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24 | * NOTE: the BSP (startup/bspstart.c) uses |
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25 | * hardcoded window lengths that match this |
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26 | * layout: |
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27 | */ |
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28 | #define _VME_A32_WIN0_ON_PCI 0x90000000 |
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29 | /* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate |
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30 | * CSR for space. |
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31 | */ |
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32 | #define _VME_CSR_ON_PCI 0x9e000000 |
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33 | #define _VME_A24_ON_PCI 0x9f000000 |
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34 | #define _VME_A16_ON_PCI 0x9fff0000 |
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35 | |
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36 | /* Reuse BAT 0 for VME */ |
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37 | #define BSP_VME_BAT_IDX 0 |
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38 | |
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39 | /* start of the A32 window on the VME bus |
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40 | * TODO: this should perhaps be a configuration option |
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41 | */ |
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42 | #define _VME_A32_WIN0_ON_VME 0x20000000 |
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43 | |
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44 | /* if _VME_DRAM_OFFSET is defined, the BSP |
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45 | * will map our RAM onto the VME bus, starting |
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46 | * at _VME_DRAM_OFFSET |
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47 | */ |
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48 | #define _VME_DRAM_OFFSET 0x90000000 |
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49 | |
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50 | #define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ |
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51 | do { \ |
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52 | err = vmeUniverseInstallIrqMgrAlt(VMEUNIVERSE_IRQ_MGR_FLAG_SHARED,\ |
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53 | 0, BSP_GPP_VME_VLINT0, \ |
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54 | 1, BSP_GPP_VME_VLINT1, \ |
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55 | 2, BSP_GPP_VME_VLINT2, \ |
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56 | 3, BSP_GPP_VME_VLINT3, \ |
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57 | -1 /* terminate list */); \ |
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58 | } while (0) |
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59 | |
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60 | #endif |
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