source: rtems/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c @ f4a59e33

4.104.114.84.95
Last change on this file since f4a59e33 was f4a59e33, checked in by Ralf Corsepius <ralf.corsepius@…>, on Oct 21, 2004 at 8:17:43 AM

2004-10-21 Ralf Corsepius <ralf_corsepius@…>

  • start/preload.S, include/bsp.h, vectors/exceptionhandler.c, startup/bspstart.c: Misc. adaptations to rtems-4.7.
  • Property mode set to 100644
File size: 17.9 KB
Line 
1/*
2 *  This routine starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before this routine is invoked.
6 *
7 *  COPYRIGHT (c) 1989-1998.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  Modified to support the MCP750.
15 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
16 *
17 *  Modified to support the Synergy VGM & Motorola PowerPC boards.
18 *  Many thanks to Till Straumann for providing assistance to port the
19 *  BSP_pgtbl_xxx().
20 *  (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004
21 *
22 *  Modified to support the MVME5500 board
23 *  (C) by S. Kate Feng <feng1@bnl.gov>, 2003, 2004
24 *
25 *  $Id$
26 */
27
28#include <string.h>
29#include <stdlib.h>
30#include <ctype.h>
31
32#include <rtems/system.h>
33#include <rtems/libio.h>
34#include <rtems/libcsupport.h>
35/*#include <bsp/consoleIo.h>*/
36#include <libcpu/spr.h>   /* registers.h is included here */
37#include <bsp.h>
38#include <bsp/uart.h>
39#include <bsp/pci.h>
40#include <libcpu/bat.h>
41#include <libcpu/pte121.h>
42#include <libcpu/cpuIdent.h>
43#include <bsp/vectors.h>
44#include <bsp/bspException.h>
45
46/* for RTEMS_VERSION :-( I dont like the preassembled string */
47#include <rtems/sptables.h>
48
49#ifdef __RTEMS_APPLICATION__
50#undef __RTEMS_APPLICATION__
51#endif
52
53/*
54#define SHOW_MORE_INIT_SETTINGS
55#define SHOW_LCR1_REGISTER
56#define SHOW_LCR2_REGISTER
57#define SHOW_LCR3_REGISTER
58#define CONF_VPD
59*/
60
61/* there is no public Workspace_Free() variant :-( */
62#include <rtems/score/wkspace.h>
63
64uint32_t
65_bsp_sbrk_init(uint32_t heap_start, uint32_t *heap_size_p);
66
67/* provide access to the command line parameters */
68char *BSP_commandline_string = 0;
69
70BSP_output_char_function_type BSP_output_char = BSP_output_char_via_serial;
71
72extern char *BSP_build_date;
73extern void _return_to_ppcbug();
74extern unsigned long __rtems_end[];
75extern void L1_caches_enables();
76extern unsigned get_L1CR(), get_L2CR(), get_L3CR();
77extern unsigned set_L2CR(unsigned);
78extern void bsp_cleanup(void);
79extern Triv121PgTbl BSP_pgtbl_setup();
80extern void BSP_pgtbl_activate();
81extern int I2Cread_eeprom();
82extern void BSP_vme_config(void);
83
84SPR_RW(SPRG0)
85SPR_RW(SPRG1)
86
87typedef struct CmdLineRec_ {
88                unsigned long   size;
89                char            buf[0];
90} CmdLineRec, *CmdLine;
91
92
93#define mtspr(reg, val) \
94        __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
95
96
97#define mfspr(reg) \
98        ( { unsigned val; \
99          __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
100          val; } )
101
102/*
103 * Copy Additional boot param passed by boot loader
104 */
105#define MAX_LOADER_ADD_PARM 80
106char loaderParam[MAX_LOADER_ADD_PARM];
107
108/*
109 * Total memory using RESIDUAL DATA
110 */
111unsigned int BSP_mem_size;
112/*
113 * PCI Bus Frequency
114 */
115unsigned int BSP_bus_frequency;
116/*
117 * processor clock frequency
118 */
119unsigned int BSP_processor_frequency;
120/*
121 * Time base divisior (how many tick for 1 second).
122 */
123unsigned int BSP_time_base_divisor;
124unsigned char ConfVPD_buff[200];
125
126/*
127 * system init stack and soft ir stack size
128 */
129#define INIT_STACK_SIZE 0x1000
130#define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY
131
132/* calculate the heap start */
133static unsigned long
134heapStart(void)
135{
136unsigned long rval;
137    rval = ((uint32_t) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE;
138    if (rval & (CPU_ALIGNMENT-1))
139        rval = (rval + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
140        return rval;
141}
142
143void BSP_panic(char *s)
144{
145  printk("%s PANIC %s\n",_RTEMS_version, s);
146  __asm__ __volatile ("sc"); 
147}
148
149void _BSP_Fatal_error(unsigned int v)
150{
151  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
152  __asm__ __volatile ("sc"); 
153}
154 
155/*
156 *  The original table from the application and our copy of it with
157 *  some changes.
158 */
159
160extern rtems_configuration_table Configuration;
161
162rtems_configuration_table  BSP_Configuration;
163
164rtems_cpu_table Cpu_table;
165
166char *rtems_progname;
167
168/*
169 *  Use the shared implementations of the following routines
170 */
171 
172extern void bsp_postdriver_hook(void); /* see c/src/lib/libbsp/shared/bsppost.c */
173
174extern void bsp_libc_init( void *, unsigned32, int );
175
176/*
177 *  Function:   bsp_pretasking_hook
178 *  Created:    95/03/10
179 *
180 *  Description:
181 *      BSP pretasking hook.  Called just before drivers are initialized.
182 *      Used to setup libc and install any BSP extensions.
183 *
184 *  NOTES:
185 *      Must not use libc (to do io) from here, since drivers are
186 *      not yet initialized.
187 *
188 */
189
190void bsp_pretasking_hook(void)
191{
192    uint32_t        heap_start=heapStart();   
193    uint32_t        heap_size,heap_sbrk_spared;
194    char                    *buf;
195    extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*);
196
197    heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
198
199    heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
200
201#ifdef SHOW_MORE_INIT_SETTINGS
202        printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared);
203#endif   
204
205    bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
206
207#ifdef RTEMS_DEBUG
208    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
209#endif
210}
211
212void zero_bss()
213{
214  /* prevent these from being accessed in the short data areas */
215  extern unsigned long __bss_start[], __sbss_start[], __sbss_end[];
216  extern unsigned long __sbss2_start[], __sbss2_end[];
217  memset(__sbss_start, 0, ((unsigned) __sbss_end) - ((unsigned)__sbss_start));
218  memset(__sbss2_start, 0, ((unsigned) __sbss2_end) - ((unsigned)__sbss2_start));
219  memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start));
220}
221
222/* NOTE: we cannot simply malloc the commandline string;
223 * save_boot_params() is called during a very early stage when
224 * libc/malloc etc. are not yet initialized!
225 *
226 * Here's what we do:
227 *
228 * initial layout setup by the loader (preload.S):
229 *
230 * 0..RTEMS...__rtems_end | cmdline ....... TOP
231 *
232 * After the save_boot_params() routine returns, the stack area will be
233 * set up (start.S):
234 *
235 * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ..... TOP
236 *
237 * initialize_executive_early() [called from boot_card()]
238 * will initialize the workspace:
239 *
240 * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ...... | workspace | TOP
241 *
242 * and later calls our pretasking_hook() which ends up initializing
243 * libc which in turn initializes the heap
244 *
245 * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | heap | workspace | TOP
246 *
247 * The idea here is to first move the commandline to the future 'heap' area
248 * from where it will be picked up by our pretasking_hook().
249 * pretasking_hook() then moves it either to INIT_STACK or the workspace
250 * area using proper allocation, initializes libc and finally moves
251 * the data to the environment / malloced areas...
252 */
253
254/* this routine is called early at shared/start/start.S
255 * and must be safe with a not properly aligned stack
256 */
257void
258save_boot_params(void *r3, void *r4, void* r5, char *cmdline_start, char *cmdline_end)
259{
260int             i=cmdline_end-cmdline_start;
261CmdLine future_heap=(CmdLine)heapStart();
262
263        /* get the string out of the stack area into the future heap region;
264         * assume there's enough memory...
265         */
266        memmove(future_heap->buf,cmdline_start,i);
267        /* make sure there's an end of string marker */
268        future_heap->buf[i++]=0;
269        future_heap->size=i;
270}
271
272
273/* Configure and enable the L3CR */
274void config_enable_L3CR(unsigned l3cr)
275{
276        unsigned x;
277
278        /* By The Book (numbered steps from section 3.7.3.1 of MPC7450UM) */                           
279        /*
280         * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and
281         *    L3CLKEN.  (also mask off reserved bits in case they were included
282         *    in L3CR_CONFIG)
283         */
284        l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_LOCK_745x|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED);
285        mtspr(L3CR, l3cr);
286
287        /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */
288        l3cr |= 0x04000000;
289        mtspr(L3CR, l3cr);
290
291        /* 3: Set L3CLKEN to 1*/
292        l3cr |= L3CR_L3CLKEN;
293        mtspr(L3CR, l3cr);
294
295        /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */
296        __asm __volatile("dssall;sync");
297        /* L3 cache is already disabled, no need to clear L3E */
298        mtspr(L3CR, l3cr|L3CR_L3I);
299
300        do {
301               x = mfspr(L3CR);
302        } while (x & L3CR_L3I);
303       
304        /* 6: Clear L3CLKEN to 0 */
305        l3cr &= ~L3CR_L3CLKEN;
306        mtspr(L3CR, l3cr);
307
308        /* 7: Perform a 'sync' and wait at least 100 CPU cycles */
309        __asm __volatile("sync");
310        rtems_bsp_delay_in_bus_cycles(100);
311
312        /* 8: Set L3E and L3CLKEN */
313        l3cr |= (L3CR_L3E|L3CR_L3CLKEN);
314        mtspr(L3CR, l3cr);
315
316        /* 9: Perform a 'sync' and wait at least 100 CPU cycles */
317        __asm __volatile("sync");
318
319        rtems_bsp_delay_in_bus_cycles(100);
320}
321
322/*
323 *  bsp_start
324 *
325 *  This routine does the bulk of the system initialization.
326 */
327
328void bsp_start( void )
329{
330  int i;
331  unsigned char *stack;
332  unsigned long  *r1sp;
333  unsigned l1cr, l2cr, l3cr;
334  register unsigned char* intrStack;
335  register unsigned int intrNestingLevel = 0;
336  unsigned char *work_space_start;
337  ppc_cpu_id_t myCpu;
338  ppc_cpu_revision_t myCpuRevision;
339  Triv121PgTbl  pt=0;
340  /*
341   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
342   * store the result in global variables so that it can be used latter...
343   */
344  myCpu         = get_ppc_cpu_type();
345  myCpuRevision = get_ppc_cpu_revision();
346
347  /*
348   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
349   * relevant CPU type so that the reason why there is no use of myCpu...
350   *
351   * MOTLoad default is good. Otherwise, one would have to disable L2, L3
352   * first before settting L1.  Then L1->L2->L3.
353   *
354   L1_caches_enables();*/
355 
356#ifdef SHOW_LCR1_REGISTER
357  l1cr = get_L1CR();
358  printk("Initial L1CR value = %x\n", l1cr); 
359#endif
360
361  /*
362   * the initial stack  has aready been set to this value in start.S
363   * so there is no need to set it in r1 again... It is just for info
364   * so that it can be printed without accessing R1.
365   */
366  stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
367
368 /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
369  *((unsigned32 *)stack) = 0;
370
371  /* fill stack with pattern for debugging */
372  __asm__ __volatile__("mr %0, %%r1":"=r"(r1sp));
373  while (--r1sp >= (unsigned long*)__rtems_end)
374          *r1sp=0xeeeeeeee;
375
376  /*
377   * Initialize the interrupt related settings
378   * SPRG0 = interrupt nesting level count
379   * SPRG1 = software managed IRQ stack
380   *
381   * This could be done latter (e.g in IRQ_INIT) but it helps to understand
382   * some settings below...
383   */
384  intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
385
386  /* make sure it's properly aligned */
387  (unsigned32)intrStack &= ~(CPU_STACK_ALIGNMENT-1);
388
389  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
390  *((unsigned32 *)intrStack) = 0;
391
392  _write_SPRG1((unsigned int)intrStack);
393  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
394
395  /*
396   * Initialize default raw exception hanlders. See vectors/vectors_init.c
397   */
398  initialize_exceptions();
399  /*
400   * Init MMU block address translation to enable hardware
401   * access
402   * More PCI1 memory mapping to be done after BSP_pgtbl_activate.
403   */
404  /*
405   * PCI 0 domain memory space, want to leave room for the VME window
406   */
407  setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE);
408
409  /* map the PCI 0, 1 Domain I/O space, GT64260B registers
410   * and the reserved area so that the size is the power of 2.
411   */
412  setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE);
413
414  printk("-----------------------------------------\n");
415  printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version );
416  printk("Build Date: %s\n",BSP_build_date);
417  printk("-----------------------------------------\n");
418
419#ifdef TEST_RETURN_TO_PPCBUG 
420  printk("Hit <Enter> to return to PPCBUG monitor\n");
421  printk("When Finished hit GO. It should print <Back from monitor>\n");
422  debug_getc();
423  _return_to_ppcbug();
424  printk("Back from monitor\n");
425  _return_to_ppcbug();
426#endif /* TEST_RETURN_TO_PPCBUG  */
427
428#ifdef TEST_RAW_EXCEPTION_CODE 
429  printk("Testing exception handling Part 1\n");
430  /*
431   * Cause a software exception
432   */
433  __asm__ __volatile ("sc");
434  /*
435   * Check we can still catch exceptions and returned coorectly.
436   */
437  printk("Testing exception handling Part 2\n");
438  __asm__ __volatile ("sc");
439#endif 
440
441  BSP_mem_size                          =  _512M;
442  /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit of System Status  register */
443  /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */
444  BSP_bus_frequency                     = 133333333;
445  BSP_processor_frequency               = 1000000000;
446  BSP_time_base_divisor                 = 4000;/* P94 : 7455 clocks the TB/DECR at 1/4 of the system bus clock frequency */
447
448
449  /* Maybe not setup yet becuase of the warning message */
450  /* Allocate and set up the page table mappings
451   * This is only available on >604 CPUs.
452   *
453   * NOTE: This setup routine may modify the available memory
454   *       size. It is essential to call it before
455   *       calculating the workspace etc.
456   */
457  pt = BSP_pgtbl_setup(&BSP_mem_size);
458  if (!pt)
459     printk("WARNING: unable to setup page tables.\n");
460
461  printk("Now BSP_mem_size = 0x%x\n",BSP_mem_size); 
462
463  /*
464   * Set up our hooks
465   * Make sure libc_init is done before drivers initialized so that
466   * they can use atexit()
467   */
468
469  Cpu_table.pretasking_hook      = bsp_pretasking_hook;    /* init libc, etc. */
470  Cpu_table.postdriver_hook      = bsp_postdriver_hook;
471  Cpu_table.do_zero_of_workspace = TRUE;
472  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
473  /* P94 : 7455 TB/DECR is clocked by the system bus clock frequency */
474  Cpu_table.clicks_per_usec      = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
475  Cpu_table.exceptions_in_RAM    = TRUE;
476  _CPU_Table                     = Cpu_table;/* <skf> for rtems_bsp_delay() */
477
478  printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size); 
479  work_space_start = 
480    (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;
481
482  if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
483    printk( "bspstart: Not enough RAM!!!\n" );
484    bsp_cleanup();
485  }
486
487  BSP_Configuration.work_space_start = work_space_start;
488
489  /*
490   * Initalize RTEMS IRQ system
491   */
492   BSP_rtems_irq_mng_init(0);
493
494  /*
495   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
496   * relevant CPU type (mpc750)...
497   *
498   * It also takes care of flushing the cache under certain conditions:
499   *   current    going to (E==enable, I==invalidate)
500   *     E           E | I      -> __NOT_FLUSHED_, invalidated, stays E
501   *     E               I      -> flush & disable, invalidate
502   *     E           E          -> nothing, stays E
503   *     0           E | I      -> not flushed, invalidated, enabled
504   *     0             | I      -> not flushed, invalidated, stays off
505   *     0           E      -> not flushed, _NO_INVALIDATE, enabled
506   *
507   * The first and the last combinations are potentially dangerous!
508   *
509   * NOTE: we assume the essential cache parameters (speed, size etc.)
510   *       have been set correctly by the firmware!
511   *
512   */
513#ifdef SHOW_LCR2_REGISTER
514  l2cr = get_L2CR();
515  printk("Initial L2CR value = %x\n", l2cr);
516#endif 
517#if 0
518  /* Again, MOTload setup seems to be fine. Otherwise, one would
519   * have to disable the L3 cahce, then R2 ->R3
520   */
521  if ( -1 != (int)l2cr ) {
522        /* -1 would mean that this machine doesn't support L2 */
523
524        l2cr &= ~( L2CR_LOCK_745x); /* clear 'data only' and 'instruction only' */
525        l2cr |= L2CR_L3OH0;    /* L3 output hold 0 should be set */
526        if ( ! (l2cr & L2CR_L2E) ) {
527            /* we are going to enable the L2 - hence we
528             * MUST invalidate it first; however, if
529             * it was enabled already, we MUST NOT
530             * invalidate it!!
531             */
532             l2cr |= L2CR_L2E | L2CR_L2I;
533             l2cr=set_L2CR(l2cr);
534        }
535        l2cr=set_L2CR(l2cr);
536  }
537#endif
538
539#ifdef SHOW_LCR3_REGISTER
540  /* L3CR needs DEC int. handler installed for bsp_delay()*/
541  l3cr = get_L3CR();
542  printk("Initial L3CR value = %x\n", l3cr);
543#endif 
544
545#if 0 
546  /* Again, use the MOTLoad default for L3CR again */
547  if ( -1 != (int)l3cr ) {
548        /* -1 would mean that this machine doesn't support L3 */
549        /* BSD : %2 , SDRAM late wirte
550           l3cr |= L3SIZ_2M|L3CLK_20|L3RT_PIPELINE_LATE; */
551        /* MOTLOad :0xDF826000-> %5, 4 clocks sample point,3 p-clocks SP */
552        l3cr |= L3CR_L3PE| L3SIZ_2M|L3CLK_50|L3CKSP_4|L3PSP_3;
553
554        /* TOCHECK MOTload had L2 cache enabled, try to set nothing first */
555        if ( !(l3cr & L3CR_L3E)) {
556           l3cr |= L3CR_L3E | L3CR_L3I;
557           config_enable_L3CR(l3cr);
558        }
559  }
560#endif
561
562  /* Activate the page table mappings only after
563   * initializing interrupts because the irq_mng_init()
564   * routine needs to modify the text
565   */           
566  if (pt) {
567#ifdef SHOW_MORE_INIT_SETTINGS
568    printk("Page table setup finished; will activate it NOW...\n");
569#endif
570    BSP_pgtbl_activate(pt);
571  }
572
573  /*
574   * PCI 1 domain memory space
575   */
576  setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE);
577 
578
579#ifdef SHOW_MORE_INIT_SETTINGS
580  printk("Going to start PCI buses scanning and initialization\n");
581#endif 
582  InitializePCI();
583#ifdef SHOW_MORE_INIT_SETTINGS
584  printk("Number of PCI buses found is : %d\n", BusCountPCI());
585#endif
586
587  /* Install our own exception handler (needs PCI) */
588  globalExceptHdl = BSP_exceptionHandler;
589
590  /* clear hostbridge errors. MCP signal is not used on the MVME5500
591   * PCI config space scanning code will trip otherwise :-(
592   */
593  _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
594
595  /*
596   * Initialize VME bridge - needs working PCI
597   * and IRQ subsystems...
598   */
599#ifdef SHOW_MORE_INIT_SETTINGS
600  printk("Going to initialize VME bridge\n");
601#endif
602  /* VME initialization is in a separate file so apps which don't use
603   * VME or want a different configuration may link against a customized
604   * routine.
605   */
606  BSP_vme_config();
607
608  /* Read Configuration Vital Product Data (VPD) */
609  if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))
610     printk("I2Cread_eeprom() error \n");
611  else {
612#ifdef CONF_VPD
613    printk("\n");
614    for (i=0; i<150; i++) {
615      printk("%2x ", ConfVPD_buff[i]); 
616      if ((i % 20)==0 ) printk("\n");
617    }
618    printk("\n");
619#endif
620  }
621
622#ifdef SHOW_MORE_INIT_SETTINGS
623  printk("MSR %x \n", _read_MSR());
624  printk("Exit from bspstart\n");
625#endif
626
627}
Note: See TracBrowser for help on using the repository browser.