source: rtems/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c @ b3a78e34

4.104.114.84.95
Last change on this file since b3a78e34 was b3a78e34, checked in by Ralf Corsepius <ralf.corsepius@…>, on Oct 21, 2004 at 12:23:15 PM

2004-10-21 Ralf Corsepius <ralf_corsepius@…>

  • Makefile.am: Build networking.rel conditionally. Reformat. Cosmetics.
  • wrapup/Makefile.am: Build networking.rel conditionally.
  • startup/bspstart.c: Eliminate RTEMS fixed size types.
  • Property mode set to 100644
File size: 17.9 KB
Line 
1/*
2 *  This routine starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before this routine is invoked.
6 *
7 *  COPYRIGHT (c) 1989-1998.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  Modified to support the MCP750.
15 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
16 *
17 *  Modified to support the Synergy VGM & Motorola PowerPC boards.
18 *  Many thanks to Till Straumann for providing assistance to port the
19 *  BSP_pgtbl_xxx().
20 *  (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004
21 *
22 *  Modified to support the MVME5500 board
23 *  (C) by S. Kate Feng <feng1@bnl.gov>, 2003, 2004
24 *
25 *  $Id$
26 */
27
28#include <string.h>
29#include <stdlib.h>
30#include <ctype.h>
31
32#include <rtems/system.h>
33#include <rtems/libio.h>
34#include <rtems/libcsupport.h>
35/*#include <bsp/consoleIo.h>*/
36#include <libcpu/spr.h>   /* registers.h is included here */
37#include <bsp.h>
38#include <bsp/uart.h>
39#include <bsp/pci.h>
40#include <libcpu/bat.h>
41#include <libcpu/pte121.h>
42#include <libcpu/cpuIdent.h>
43#include <bsp/vectors.h>
44#include <bsp/bspException.h>
45
46/* for RTEMS_VERSION :-( I dont like the preassembled string */
47#include <rtems/sptables.h>
48
49#ifdef __RTEMS_APPLICATION__
50#undef __RTEMS_APPLICATION__
51#endif
52
53/*
54#define SHOW_MORE_INIT_SETTINGS
55#define SHOW_LCR1_REGISTER
56#define SHOW_LCR2_REGISTER
57#define SHOW_LCR3_REGISTER
58#define CONF_VPD
59*/
60
61/* there is no public Workspace_Free() variant :-( */
62#include <rtems/score/wkspace.h>
63
64uint32_t
65_bsp_sbrk_init(uint32_t heap_start, uint32_t *heap_size_p);
66
67/* provide access to the command line parameters */
68char *BSP_commandline_string = 0;
69
70BSP_output_char_function_type BSP_output_char = BSP_output_char_via_serial;
71
72extern void _return_to_ppcbug();
73extern unsigned long __rtems_end[];
74extern void L1_caches_enables();
75extern unsigned get_L1CR(), get_L2CR(), get_L3CR();
76extern unsigned set_L2CR(unsigned);
77extern void bsp_cleanup(void);
78extern Triv121PgTbl BSP_pgtbl_setup();
79extern void BSP_pgtbl_activate();
80extern int I2Cread_eeprom();
81extern void BSP_vme_config(void);
82
83SPR_RW(SPRG0)
84SPR_RW(SPRG1)
85
86typedef struct CmdLineRec_ {
87                unsigned long   size;
88                char            buf[0];
89} CmdLineRec, *CmdLine;
90
91
92#define mtspr(reg, val) \
93        __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
94
95
96#define mfspr(reg) \
97        ( { unsigned val; \
98          __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
99          val; } )
100
101/*
102 * Copy Additional boot param passed by boot loader
103 */
104#define MAX_LOADER_ADD_PARM 80
105char loaderParam[MAX_LOADER_ADD_PARM];
106
107/*
108 * Total memory using RESIDUAL DATA
109 */
110unsigned int BSP_mem_size;
111/*
112 * PCI Bus Frequency
113 */
114unsigned int BSP_bus_frequency;
115/*
116 * processor clock frequency
117 */
118unsigned int BSP_processor_frequency;
119/*
120 * Time base divisior (how many tick for 1 second).
121 */
122unsigned int BSP_time_base_divisor;
123unsigned char ConfVPD_buff[200];
124
125/*
126 * system init stack and soft ir stack size
127 */
128#define INIT_STACK_SIZE 0x1000
129#define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY
130
131/* calculate the heap start */
132static unsigned long
133heapStart(void)
134{
135unsigned long rval;
136    rval = ((uint32_t) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE;
137    if (rval & (CPU_ALIGNMENT-1))
138        rval = (rval + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
139        return rval;
140}
141
142void BSP_panic(char *s)
143{
144  printk("%s PANIC %s\n",_RTEMS_version, s);
145  __asm__ __volatile ("sc"); 
146}
147
148void _BSP_Fatal_error(unsigned int v)
149{
150  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
151  __asm__ __volatile ("sc"); 
152}
153 
154/*
155 *  The original table from the application and our copy of it with
156 *  some changes.
157 */
158
159extern rtems_configuration_table Configuration;
160
161rtems_configuration_table  BSP_Configuration;
162
163rtems_cpu_table Cpu_table;
164
165char *rtems_progname;
166
167/*
168 *  Use the shared implementations of the following routines
169 */
170 
171extern void bsp_postdriver_hook(void); /* see c/src/lib/libbsp/shared/bsppost.c */
172
173extern void bsp_libc_init( void *, uint32_t, int );
174
175/*
176 *  Function:   bsp_pretasking_hook
177 *  Created:    95/03/10
178 *
179 *  Description:
180 *      BSP pretasking hook.  Called just before drivers are initialized.
181 *      Used to setup libc and install any BSP extensions.
182 *
183 *  NOTES:
184 *      Must not use libc (to do io) from here, since drivers are
185 *      not yet initialized.
186 *
187 */
188
189void bsp_pretasking_hook(void)
190{
191    uint32_t        heap_start=heapStart();   
192    uint32_t        heap_size,heap_sbrk_spared;
193    char                    *buf;
194    extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*);
195
196    heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
197
198    heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
199
200#ifdef SHOW_MORE_INIT_SETTINGS
201        printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared);
202#endif   
203
204    bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
205
206#ifdef RTEMS_DEBUG
207    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
208#endif
209}
210
211void zero_bss()
212{
213  /* prevent these from being accessed in the short data areas */
214  extern unsigned long __bss_start[], __sbss_start[], __sbss_end[];
215  extern unsigned long __sbss2_start[], __sbss2_end[];
216  memset(__sbss_start, 0, ((unsigned) __sbss_end) - ((unsigned)__sbss_start));
217  memset(__sbss2_start, 0, ((unsigned) __sbss2_end) - ((unsigned)__sbss2_start));
218  memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start));
219}
220
221/* NOTE: we cannot simply malloc the commandline string;
222 * save_boot_params() is called during a very early stage when
223 * libc/malloc etc. are not yet initialized!
224 *
225 * Here's what we do:
226 *
227 * initial layout setup by the loader (preload.S):
228 *
229 * 0..RTEMS...__rtems_end | cmdline ....... TOP
230 *
231 * After the save_boot_params() routine returns, the stack area will be
232 * set up (start.S):
233 *
234 * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ..... TOP
235 *
236 * initialize_executive_early() [called from boot_card()]
237 * will initialize the workspace:
238 *
239 * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ...... | workspace | TOP
240 *
241 * and later calls our pretasking_hook() which ends up initializing
242 * libc which in turn initializes the heap
243 *
244 * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | heap | workspace | TOP
245 *
246 * The idea here is to first move the commandline to the future 'heap' area
247 * from where it will be picked up by our pretasking_hook().
248 * pretasking_hook() then moves it either to INIT_STACK or the workspace
249 * area using proper allocation, initializes libc and finally moves
250 * the data to the environment / malloced areas...
251 */
252
253/* this routine is called early at shared/start/start.S
254 * and must be safe with a not properly aligned stack
255 */
256void
257save_boot_params(void *r3, void *r4, void* r5, char *cmdline_start, char *cmdline_end)
258{
259int             i=cmdline_end-cmdline_start;
260CmdLine future_heap=(CmdLine)heapStart();
261
262        /* get the string out of the stack area into the future heap region;
263         * assume there's enough memory...
264         */
265        memmove(future_heap->buf,cmdline_start,i);
266        /* make sure there's an end of string marker */
267        future_heap->buf[i++]=0;
268        future_heap->size=i;
269}
270
271
272/* Configure and enable the L3CR */
273void config_enable_L3CR(unsigned l3cr)
274{
275        unsigned x;
276
277        /* By The Book (numbered steps from section 3.7.3.1 of MPC7450UM) */                           
278        /*
279         * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and
280         *    L3CLKEN.  (also mask off reserved bits in case they were included
281         *    in L3CR_CONFIG)
282         */
283        l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_LOCK_745x|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED);
284        mtspr(L3CR, l3cr);
285
286        /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */
287        l3cr |= 0x04000000;
288        mtspr(L3CR, l3cr);
289
290        /* 3: Set L3CLKEN to 1*/
291        l3cr |= L3CR_L3CLKEN;
292        mtspr(L3CR, l3cr);
293
294        /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */
295        __asm __volatile("dssall;sync");
296        /* L3 cache is already disabled, no need to clear L3E */
297        mtspr(L3CR, l3cr|L3CR_L3I);
298
299        do {
300               x = mfspr(L3CR);
301        } while (x & L3CR_L3I);
302       
303        /* 6: Clear L3CLKEN to 0 */
304        l3cr &= ~L3CR_L3CLKEN;
305        mtspr(L3CR, l3cr);
306
307        /* 7: Perform a 'sync' and wait at least 100 CPU cycles */
308        __asm __volatile("sync");
309        rtems_bsp_delay_in_bus_cycles(100);
310
311        /* 8: Set L3E and L3CLKEN */
312        l3cr |= (L3CR_L3E|L3CR_L3CLKEN);
313        mtspr(L3CR, l3cr);
314
315        /* 9: Perform a 'sync' and wait at least 100 CPU cycles */
316        __asm __volatile("sync");
317
318        rtems_bsp_delay_in_bus_cycles(100);
319}
320
321/*
322 *  bsp_start
323 *
324 *  This routine does the bulk of the system initialization.
325 */
326
327void bsp_start( void )
328{
329  int i;
330  unsigned char *stack;
331  unsigned long  *r1sp;
332  unsigned l1cr, l2cr, l3cr;
333  register unsigned char* intrStack;
334  register unsigned int intrNestingLevel = 0;
335  unsigned char *work_space_start;
336  ppc_cpu_id_t myCpu;
337  ppc_cpu_revision_t myCpuRevision;
338  Triv121PgTbl  pt=0;
339  /*
340   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
341   * store the result in global variables so that it can be used latter...
342   */
343  myCpu         = get_ppc_cpu_type();
344  myCpuRevision = get_ppc_cpu_revision();
345
346  /*
347   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
348   * relevant CPU type so that the reason why there is no use of myCpu...
349   *
350   * MOTLoad default is good. Otherwise, one would have to disable L2, L3
351   * first before settting L1.  Then L1->L2->L3.
352   *
353   L1_caches_enables();*/
354 
355#ifdef SHOW_LCR1_REGISTER
356  l1cr = get_L1CR();
357  printk("Initial L1CR value = %x\n", l1cr); 
358#endif
359
360  /*
361   * the initial stack  has aready been set to this value in start.S
362   * so there is no need to set it in r1 again... It is just for info
363   * so that it can be printed without accessing R1.
364   */
365  stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
366
367 /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
368  *((uint32_t *)stack) = 0;
369
370  /* fill stack with pattern for debugging */
371  __asm__ __volatile__("mr %0, %%r1":"=r"(r1sp));
372  while (--r1sp >= (unsigned long*)__rtems_end)
373          *r1sp=0xeeeeeeee;
374
375  /*
376   * Initialize the interrupt related settings
377   * SPRG0 = interrupt nesting level count
378   * SPRG1 = software managed IRQ stack
379   *
380   * This could be done latter (e.g in IRQ_INIT) but it helps to understand
381   * some settings below...
382   */
383  intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
384
385  /* make sure it's properly aligned */
386  (uint32_t)intrStack &= ~(CPU_STACK_ALIGNMENT-1);
387
388  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
389  *((uint32_t *)intrStack) = 0;
390
391  _write_SPRG1((unsigned int)intrStack);
392  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
393
394  /*
395   * Initialize default raw exception hanlders. See vectors/vectors_init.c
396   */
397  initialize_exceptions();
398  /*
399   * Init MMU block address translation to enable hardware
400   * access
401   * More PCI1 memory mapping to be done after BSP_pgtbl_activate.
402   */
403  /*
404   * PCI 0 domain memory space, want to leave room for the VME window
405   */
406  setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE);
407
408  /* map the PCI 0, 1 Domain I/O space, GT64260B registers
409   * and the reserved area so that the size is the power of 2.
410   */
411  setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE);
412
413  printk("-----------------------------------------\n");
414  printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version );
415  printk("-----------------------------------------\n");
416
417#ifdef TEST_RETURN_TO_PPCBUG 
418  printk("Hit <Enter> to return to PPCBUG monitor\n");
419  printk("When Finished hit GO. It should print <Back from monitor>\n");
420  debug_getc();
421  _return_to_ppcbug();
422  printk("Back from monitor\n");
423  _return_to_ppcbug();
424#endif /* TEST_RETURN_TO_PPCBUG  */
425
426#ifdef TEST_RAW_EXCEPTION_CODE 
427  printk("Testing exception handling Part 1\n");
428  /*
429   * Cause a software exception
430   */
431  __asm__ __volatile ("sc");
432  /*
433   * Check we can still catch exceptions and returned coorectly.
434   */
435  printk("Testing exception handling Part 2\n");
436  __asm__ __volatile ("sc");
437#endif 
438
439  BSP_mem_size                          =  _512M;
440  /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit of System Status  register */
441  /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */
442  BSP_bus_frequency                     = 133333333;
443  BSP_processor_frequency               = 1000000000;
444  BSP_time_base_divisor                 = 4000;/* P94 : 7455 clocks the TB/DECR at 1/4 of the system bus clock frequency */
445
446
447  /* Maybe not setup yet becuase of the warning message */
448  /* Allocate and set up the page table mappings
449   * This is only available on >604 CPUs.
450   *
451   * NOTE: This setup routine may modify the available memory
452   *       size. It is essential to call it before
453   *       calculating the workspace etc.
454   */
455  pt = BSP_pgtbl_setup(&BSP_mem_size);
456  if (!pt)
457     printk("WARNING: unable to setup page tables.\n");
458
459  printk("Now BSP_mem_size = 0x%x\n",BSP_mem_size); 
460
461  /*
462   * Set up our hooks
463   * Make sure libc_init is done before drivers initialized so that
464   * they can use atexit()
465   */
466
467  Cpu_table.pretasking_hook      = bsp_pretasking_hook;    /* init libc, etc. */
468  Cpu_table.postdriver_hook      = bsp_postdriver_hook;
469  Cpu_table.do_zero_of_workspace = TRUE;
470  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
471  /* P94 : 7455 TB/DECR is clocked by the system bus clock frequency */
472  Cpu_table.clicks_per_usec      = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
473  Cpu_table.exceptions_in_RAM    = TRUE;
474  _CPU_Table                     = Cpu_table;/* <skf> for rtems_bsp_delay() */
475
476  printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size); 
477  work_space_start = 
478    (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;
479
480  if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
481    printk( "bspstart: Not enough RAM!!!\n" );
482    bsp_cleanup();
483  }
484
485  BSP_Configuration.work_space_start = work_space_start;
486
487  /*
488   * Initalize RTEMS IRQ system
489   */
490   BSP_rtems_irq_mng_init(0);
491
492  /*
493   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
494   * relevant CPU type (mpc750)...
495   *
496   * It also takes care of flushing the cache under certain conditions:
497   *   current    going to (E==enable, I==invalidate)
498   *     E           E | I      -> __NOT_FLUSHED_, invalidated, stays E
499   *     E               I      -> flush & disable, invalidate
500   *     E           E          -> nothing, stays E
501   *     0           E | I      -> not flushed, invalidated, enabled
502   *     0             | I      -> not flushed, invalidated, stays off
503   *     0           E      -> not flushed, _NO_INVALIDATE, enabled
504   *
505   * The first and the last combinations are potentially dangerous!
506   *
507   * NOTE: we assume the essential cache parameters (speed, size etc.)
508   *       have been set correctly by the firmware!
509   *
510   */
511#ifdef SHOW_LCR2_REGISTER
512  l2cr = get_L2CR();
513  printk("Initial L2CR value = %x\n", l2cr);
514#endif 
515#if 0
516  /* Again, MOTload setup seems to be fine. Otherwise, one would
517   * have to disable the L3 cahce, then R2 ->R3
518   */
519  if ( -1 != (int)l2cr ) {
520        /* -1 would mean that this machine doesn't support L2 */
521
522        l2cr &= ~( L2CR_LOCK_745x); /* clear 'data only' and 'instruction only' */
523        l2cr |= L2CR_L3OH0;    /* L3 output hold 0 should be set */
524        if ( ! (l2cr & L2CR_L2E) ) {
525            /* we are going to enable the L2 - hence we
526             * MUST invalidate it first; however, if
527             * it was enabled already, we MUST NOT
528             * invalidate it!!
529             */
530             l2cr |= L2CR_L2E | L2CR_L2I;
531             l2cr=set_L2CR(l2cr);
532        }
533        l2cr=set_L2CR(l2cr);
534  }
535#endif
536
537#ifdef SHOW_LCR3_REGISTER
538  /* L3CR needs DEC int. handler installed for bsp_delay()*/
539  l3cr = get_L3CR();
540  printk("Initial L3CR value = %x\n", l3cr);
541#endif 
542
543#if 0 
544  /* Again, use the MOTLoad default for L3CR again */
545  if ( -1 != (int)l3cr ) {
546        /* -1 would mean that this machine doesn't support L3 */
547        /* BSD : %2 , SDRAM late wirte
548           l3cr |= L3SIZ_2M|L3CLK_20|L3RT_PIPELINE_LATE; */
549        /* MOTLOad :0xDF826000-> %5, 4 clocks sample point,3 p-clocks SP */
550        l3cr |= L3CR_L3PE| L3SIZ_2M|L3CLK_50|L3CKSP_4|L3PSP_3;
551
552        /* TOCHECK MOTload had L2 cache enabled, try to set nothing first */
553        if ( !(l3cr & L3CR_L3E)) {
554           l3cr |= L3CR_L3E | L3CR_L3I;
555           config_enable_L3CR(l3cr);
556        }
557  }
558#endif
559
560  /* Activate the page table mappings only after
561   * initializing interrupts because the irq_mng_init()
562   * routine needs to modify the text
563   */           
564  if (pt) {
565#ifdef SHOW_MORE_INIT_SETTINGS
566    printk("Page table setup finished; will activate it NOW...\n");
567#endif
568    BSP_pgtbl_activate(pt);
569  }
570
571  /*
572   * PCI 1 domain memory space
573   */
574  setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE);
575 
576
577#ifdef SHOW_MORE_INIT_SETTINGS
578  printk("Going to start PCI buses scanning and initialization\n");
579#endif 
580  InitializePCI();
581#ifdef SHOW_MORE_INIT_SETTINGS
582  printk("Number of PCI buses found is : %d\n", BusCountPCI());
583#endif
584
585  /* Install our own exception handler (needs PCI) */
586  globalExceptHdl = BSP_exceptionHandler;
587
588  /* clear hostbridge errors. MCP signal is not used on the MVME5500
589   * PCI config space scanning code will trip otherwise :-(
590   */
591  _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
592
593  /*
594   * Initialize VME bridge - needs working PCI
595   * and IRQ subsystems...
596   */
597#ifdef SHOW_MORE_INIT_SETTINGS
598  printk("Going to initialize VME bridge\n");
599#endif
600  /* VME initialization is in a separate file so apps which don't use
601   * VME or want a different configuration may link against a customized
602   * routine.
603   */
604  BSP_vme_config();
605
606  /* Read Configuration Vital Product Data (VPD) */
607  if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))
608     printk("I2Cread_eeprom() error \n");
609  else {
610#ifdef CONF_VPD
611    printk("\n");
612    for (i=0; i<150; i++) {
613      printk("%2x ", ConfVPD_buff[i]); 
614      if ((i % 20)==0 ) printk("\n");
615    }
616    printk("\n");
617#endif
618  }
619
620#ifdef SHOW_MORE_INIT_SETTINGS
621  printk("MSR %x \n", _read_MSR());
622  printk("Exit from bspstart\n");
623#endif
624
625}
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