1 | /* |
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2 | * This routine starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before this routine is invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2007. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * Modified to support the MCP750. |
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15 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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16 | * |
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17 | * Modified to support the Synergy VGM & Motorola PowerPC boards |
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18 | * (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004, 2005 |
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19 | * |
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20 | * Modified to support the MVME5500 board. |
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21 | * Also, the settings of L1, L2, and L3 caches is not necessary here. |
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22 | * (C) by Brookhaven National Lab., S. Kate Feng <feng1@bnl.gov>, 2003-2007 |
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23 | * |
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24 | * $Id$ |
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25 | */ |
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26 | |
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27 | #include <string.h> |
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28 | #include <stdlib.h> |
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29 | #include <ctype.h> |
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30 | |
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31 | #include <rtems/system.h> |
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32 | #include <rtems/libio.h> |
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33 | #include <rtems/libcsupport.h> |
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34 | #include <rtems/powerpc/powerpc.h> |
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35 | |
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36 | #include <libcpu/spr.h> /* registers.h is included here */ |
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37 | #include <bsp.h> |
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38 | #include <bsp/uart.h> |
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39 | #include <bsp/pci.h> |
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40 | #include <libcpu/bat.h> |
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41 | #include <libcpu/pte121.h> |
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42 | #include <libcpu/cpuIdent.h> |
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43 | #include <bsp/vectors.h> |
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44 | #include <bsp/bspException.h> |
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45 | |
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46 | #include <rtems/bspIo.h> |
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47 | #include <rtems/sptables.h> |
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48 | |
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49 | #ifdef __RTEMS_APPLICATION__ |
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50 | #undef __RTEMS_APPLICATION__ |
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51 | #endif |
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52 | |
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53 | /* |
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54 | #define SHOW_MORE_INIT_SETTINGS |
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55 | #define SHOW_LCR1_REGISTER |
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56 | #define SHOW_LCR2_REGISTER |
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57 | #define SHOW_LCR3_REGISTER |
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58 | #define CONF_VPD |
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59 | */ |
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60 | |
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61 | /* there is no public Workspace_Free() variant :-( */ |
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62 | #include <rtems/score/wkspace.h> |
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63 | |
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64 | BSP_output_char_function_type BSP_output_char = BSP_output_char_via_serial; |
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65 | |
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66 | extern void _return_to_ppcbug(); |
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67 | extern unsigned long __rtems_end[]; |
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68 | extern unsigned get_L1CR(), get_L2CR(), get_L3CR(); |
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69 | extern void bsp_cleanup(void); |
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70 | extern Triv121PgTbl BSP_pgtbl_setup(); |
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71 | extern void BSP_pgtbl_activate(); |
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72 | extern int I2Cread_eeprom(); |
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73 | extern void BSP_vme_config(void); |
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74 | |
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75 | uint32_t bsp_clicks_per_usec; |
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76 | |
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77 | SPR_RW(SPRG0) |
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78 | SPR_RW(SPRG1) |
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79 | |
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80 | typedef struct CmdLineRec_ { |
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81 | unsigned long size; |
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82 | char buf[0]; |
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83 | } CmdLineRec, *CmdLine; |
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84 | |
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85 | |
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86 | #define mtspr(reg, val) \ |
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87 | __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) |
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88 | |
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89 | |
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90 | #define mfspr(reg) \ |
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91 | ( { unsigned val; \ |
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92 | __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ |
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93 | val; } ) |
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94 | |
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95 | /* |
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96 | * Copy Additional boot param passed by boot loader |
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97 | */ |
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98 | #define MAX_LOADER_ADD_PARM 80 |
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99 | char loaderParam[MAX_LOADER_ADD_PARM]; |
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100 | |
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101 | /* |
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102 | * Total memory using RESIDUAL DATA |
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103 | */ |
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104 | unsigned int BSP_mem_size; |
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105 | /* |
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106 | * PCI Bus Frequency |
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107 | */ |
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108 | /* |
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109 | * Start of the heap |
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110 | */ |
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111 | unsigned int BSP_heap_start; |
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112 | |
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113 | unsigned int BSP_bus_frequency; |
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114 | /* |
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115 | * processor clock frequency |
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116 | */ |
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117 | unsigned int BSP_processor_frequency; |
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118 | /* |
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119 | * Time base divisior (how many tick for 1 second). |
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120 | */ |
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121 | unsigned int BSP_time_base_divisor; |
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122 | unsigned char ConfVPD_buff[200]; |
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123 | |
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124 | #define CMDLINE_BUF_SIZE 2048 |
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125 | |
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126 | static char cmdline_buf[CMDLINE_BUF_SIZE]; |
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127 | char *BSP_commandline_string = cmdline_buf; |
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128 | |
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129 | /* |
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130 | * system init stack |
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131 | */ |
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132 | #define INIT_STACK_SIZE 0x1000 |
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133 | |
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134 | void BSP_panic(char *s) |
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135 | { |
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136 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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137 | __asm__ __volatile ("sc"); |
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138 | } |
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139 | |
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140 | void _BSP_Fatal_error(unsigned int v) |
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141 | { |
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142 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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143 | __asm__ __volatile ("sc"); |
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144 | } |
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145 | |
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146 | /* |
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147 | * Use the shared implementations of the following routines |
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148 | */ |
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149 | |
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150 | extern void bsp_postdriver_hook(void); /* see c/src/lib/libbsp/shared/bsppost.c */ |
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151 | |
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152 | extern void bsp_libc_init( void *, uint32_t, int ); |
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153 | |
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154 | extern void bsp_pretasking_hook(void); |
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155 | |
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156 | void zero_bss() |
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157 | { |
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158 | /* prevent these from being accessed in the short data areas */ |
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159 | extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[]; |
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160 | extern unsigned long __SBSS2_START__[], __SBSS2_END__[]; |
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161 | |
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162 | memset( |
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163 | __SBSS_START__, |
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164 | 0, |
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165 | ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__) |
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166 | ); |
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167 | memset( |
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168 | __SBSS2_START__, |
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169 | 0, |
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170 | ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__) |
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171 | ); |
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172 | memset( |
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173 | __bss_start, |
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174 | 0, |
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175 | ((unsigned) __rtems_end) - ((unsigned)__bss_start) |
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176 | ); |
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177 | } |
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178 | |
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179 | /* NOTE: we cannot simply malloc the commandline string; |
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180 | * save_boot_params() is called during a very early stage when |
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181 | * libc/malloc etc. are not yet initialized! |
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182 | * |
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183 | * Here's what we do: |
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184 | * |
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185 | * initial layout setup by the loader (preload.S): |
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186 | * |
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187 | * 0..RTEMS...__rtems_end | cmdline ....... TOP |
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188 | * |
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189 | * After the save_boot_params() routine returns, the stack area will be |
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190 | * set up (start.S): |
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191 | * |
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192 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ..... TOP |
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193 | * |
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194 | * initialize_executive_early() [called from boot_card()] |
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195 | * will initialize the workspace: |
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196 | * |
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197 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ...... | workspace | TOP |
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198 | * |
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199 | * and later calls our pretasking_hook() which ends up initializing |
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200 | * libc which in turn initializes the heap |
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201 | * |
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202 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | heap | workspace | TOP |
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203 | * |
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204 | * The idea here is to first move the commandline to the future 'heap' area |
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205 | * from where it will be picked up by our pretasking_hook(). |
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206 | * pretasking_hook() then moves it either to INIT_STACK or the workspace |
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207 | * area using proper allocation, initializes libc and finally moves |
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208 | * the data to the environment / malloced areas... |
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209 | */ |
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210 | |
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211 | /* this routine is called early at shared/start/start.S |
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212 | * and must be safe with a not properly aligned stack |
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213 | */ |
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214 | void |
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215 | save_boot_params( |
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216 | void *r3, |
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217 | void *r4, |
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218 | void* r5, |
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219 | char *cmdline_start, |
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220 | char *cmdline_end |
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221 | ) |
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222 | { |
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223 | int i=cmdline_end-cmdline_start; |
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224 | |
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225 | if ( i >= CMDLINE_BUF_SIZE ) |
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226 | i = CMDLINE_BUF_SIZE-1; |
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227 | else if ( i < 0 ) |
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228 | i = 0; |
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229 | |
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230 | memmove(cmdline_buf, cmdline_start, i); |
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231 | cmdline_buf[i]=0; |
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232 | } |
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233 | |
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234 | /* |
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235 | * bsp_start |
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236 | * |
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237 | * This routine does the bulk of the system initialization. |
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238 | */ |
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239 | |
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240 | void bsp_start( void ) |
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241 | { |
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242 | #ifdef CONF_VPD |
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243 | int i; |
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244 | #endif |
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245 | unsigned char *stack; |
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246 | unsigned long *r1sp; |
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247 | #ifdef SHOW_LCR1_REGISTER |
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248 | unsigned l1cr; |
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249 | #endif |
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250 | #ifdef SHOW_LCR2_REGISTER |
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251 | unsigned l2cr; |
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252 | #endif |
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253 | #ifdef SHOW_LCR3_REGISTER |
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254 | unsigned l3cr; |
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255 | #endif |
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256 | register uint32_t intrStack; |
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257 | register uint32_t *intrStackPtr; |
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258 | unsigned char *work_space_start; |
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259 | ppc_cpu_id_t myCpu; |
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260 | ppc_cpu_revision_t myCpuRevision; |
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261 | Triv121PgTbl pt=0; |
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262 | |
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263 | /* Till Straumann: 4/2005 |
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264 | * Need to map the system registers early, so we can printk... |
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265 | * (otherwise we silently die) |
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266 | */ |
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267 | /* |
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268 | * Kate Feng : PCI 0 domain memory space, want to leave room for the VME window |
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269 | */ |
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270 | setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE); |
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271 | |
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272 | /* Till Straumann: 2004 |
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273 | * map the PCI 0, 1 Domain I/O space, GT64260B registers |
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274 | * and the reserved area so that the size is the power of 2. |
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275 | * |
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276 | */ |
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277 | setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE); |
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278 | |
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279 | |
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280 | /* |
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281 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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282 | * store the result in global variables so that it can be used latter... |
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283 | */ |
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284 | myCpu = get_ppc_cpu_type(); |
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285 | myCpuRevision = get_ppc_cpu_revision(); |
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286 | |
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287 | #ifdef SHOW_LCR1_REGISTER |
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288 | l1cr = get_L1CR(); |
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289 | printk("Initial L1CR value = %x\n", l1cr); |
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290 | #endif |
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291 | |
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292 | /* |
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293 | * the initial stack has aready been set to this value in start.S |
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294 | * so there is no need to set it in r1 again... It is just for info |
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295 | * so that it can be printed without accessing R1. |
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296 | */ |
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297 | stack = ((unsigned char*) __rtems_end) + |
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298 | INIT_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE; |
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299 | |
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300 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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301 | *((uint32_t *)stack) = 0; |
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302 | |
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303 | /* fill stack with pattern for debugging */ |
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304 | __asm__ __volatile__("mr %0, %%r1":"=r"(r1sp)); |
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305 | while (--r1sp >= (unsigned long*)__rtems_end) |
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306 | *r1sp=0xeeeeeeee; |
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307 | |
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308 | /* |
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309 | * Initialize the interrupt related settings |
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310 | * SPRG0 = interrupt nesting level count |
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311 | * SPRG1 = software managed IRQ stack |
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312 | * |
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313 | * This could be done latter (e.g in IRQ_INIT) but it helps to understand |
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314 | * some settings below... |
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315 | */ |
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316 | BSP_heap_start = ((uint32_t) __rtems_end) + INIT_STACK_SIZE + |
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317 | rtems_configuration_get_interrupt_stack_size(); |
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318 | intrStack = BSP_heap_start - PPC_MINIMUM_STACK_FRAME_SIZE; |
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319 | |
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320 | /* make sure it's properly aligned */ |
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321 | intrStack &= ~(CPU_STACK_ALIGNMENT-1); |
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322 | |
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323 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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324 | intrStackPtr = (uint32_t*) intrStack; |
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325 | *intrStackPtr = 0; |
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326 | |
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327 | _write_SPRG1(intrStack); |
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328 | |
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329 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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330 | |
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331 | /* |
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332 | * Initialize default raw exception hanlders. See vectors/vectors_init.c |
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333 | */ |
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334 | initialize_exceptions(); |
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335 | |
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336 | /* |
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337 | * Init MMU block address translation to enable hardware |
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338 | * access |
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339 | * More PCI1 memory mapping to be done after BSP_pgtbl_activate. |
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340 | */ |
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341 | printk("-----------------------------------------\n"); |
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342 | printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version ); |
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343 | printk("-----------------------------------------\n"); |
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344 | |
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345 | #ifdef TEST_RETURN_TO_PPCBUG |
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346 | printk("Hit <Enter> to return to PPCBUG monitor\n"); |
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347 | printk("When Finished hit GO. It should print <Back from monitor>\n"); |
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348 | debug_getc(); |
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349 | _return_to_ppcbug(); |
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350 | printk("Back from monitor\n"); |
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351 | _return_to_ppcbug(); |
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352 | #endif /* TEST_RETURN_TO_PPCBUG */ |
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353 | |
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354 | #ifdef TEST_RAW_EXCEPTION_CODE |
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355 | printk("Testing exception handling Part 1\n"); |
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356 | /* |
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357 | * Cause a software exception |
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358 | */ |
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359 | __asm__ __volatile ("sc"); |
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360 | /* |
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361 | * Check we can still catch exceptions and returned coorectly. |
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362 | */ |
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363 | printk("Testing exception handling Part 2\n"); |
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364 | __asm__ __volatile ("sc"); |
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365 | #endif |
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366 | |
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367 | BSP_mem_size = _512M; |
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368 | /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit |
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369 | * of System Status register |
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370 | */ |
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371 | /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */ |
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372 | BSP_bus_frequency = 133333333; |
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373 | BSP_processor_frequency = 1000000000; |
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374 | /* P94 : 7455 clocks the TB/DECR at 1/4 of the system bus clock frequency */ |
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375 | BSP_time_base_divisor = 4000; |
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376 | |
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377 | |
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378 | /* Maybe not setup yet becuase of the warning message */ |
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379 | /* Allocate and set up the page table mappings |
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380 | * This is only available on >604 CPUs. |
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381 | * |
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382 | * NOTE: This setup routine may modify the available memory |
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383 | * size. It is essential to call it before |
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384 | * calculating the workspace etc. |
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385 | */ |
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386 | pt = BSP_pgtbl_setup(&BSP_mem_size); |
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387 | if (!pt) |
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388 | printk("WARNING: unable to setup page tables.\n"); |
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389 | |
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390 | printk("Now BSP_mem_size = 0x%x\n",BSP_mem_size); |
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391 | |
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392 | /* P94 : 7455 TB/DECR is clocked by the system bus clock frequency */ |
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393 | |
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394 | bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); |
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395 | |
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396 | printk( |
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397 | "rtems_configuration_get_work_space_size() = %x\n", |
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398 | rtems_configuration_get_work_space_size() |
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399 | ); |
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400 | |
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401 | work_space_start = |
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402 | (unsigned char *)BSP_mem_size - rtems_configuration_get_work_space_size(); |
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403 | |
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404 | if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + |
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405 | rtems_configuration_get_interrupt_stack_size()) { |
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406 | printk( "bspstart: Not enough RAM!!!\n" ); |
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407 | bsp_cleanup(); |
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408 | } |
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409 | |
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410 | Configuration.work_space_start = work_space_start; |
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411 | |
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412 | /* |
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413 | * Initalize RTEMS IRQ system |
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414 | */ |
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415 | BSP_rtems_irq_mng_init(0); |
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416 | |
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417 | #ifdef SHOW_LCR2_REGISTER |
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418 | l2cr = get_L2CR(); |
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419 | printk("Initial L2CR value = %x\n", l2cr); |
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420 | #endif |
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421 | |
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422 | #ifdef SHOW_LCR3_REGISTER |
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423 | /* L3CR needs DEC int. handler installed for bsp_delay()*/ |
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424 | l3cr = get_L3CR(); |
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425 | printk("Initial L3CR value = %x\n", l3cr); |
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426 | #endif |
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427 | |
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428 | |
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429 | /* Activate the page table mappings only after |
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430 | * initializing interrupts because the irq_mng_init() |
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431 | * routine needs to modify the text |
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432 | */ |
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433 | if (pt) { |
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434 | #ifdef SHOW_MORE_INIT_SETTINGS |
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435 | printk("Page table setup finished; will activate it NOW...\n"); |
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436 | #endif |
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437 | BSP_pgtbl_activate(pt); |
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438 | } |
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439 | |
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440 | /* |
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441 | * PCI 1 domain memory space |
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442 | */ |
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443 | setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE); |
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444 | |
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445 | |
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446 | #ifdef SHOW_MORE_INIT_SETTINGS |
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447 | printk("Going to start PCI buses scanning and initialization\n"); |
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448 | #endif |
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449 | pci_initialize(); |
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450 | #ifdef SHOW_MORE_INIT_SETTINGS |
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451 | printk("Number of PCI buses found is : %d\n", pci_bus_count()); |
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452 | #endif |
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453 | |
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454 | /* Install our own exception handler (needs PCI) */ |
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455 | globalExceptHdl = BSP_exceptionHandler; |
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456 | |
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457 | /* clear hostbridge errors. MCP signal is not used on the MVME5500 |
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458 | * PCI config space scanning code will trip otherwise :-( |
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459 | */ |
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460 | _BSP_clear_hostbridge_errors(0, 1 /*quiet*/); |
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461 | |
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462 | /* Read Configuration Vital Product Data (VPD) */ |
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463 | if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150)) |
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464 | printk("I2Cread_eeprom() error \n"); |
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465 | else { |
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466 | #ifdef CONF_VPD |
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467 | printk("\n"); |
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468 | for (i=0; i<150; i++) { |
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469 | printk("%2x ", ConfVPD_buff[i]); |
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470 | if ((i % 20)==0 ) printk("\n"); |
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471 | } |
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472 | printk("\n"); |
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473 | #endif |
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474 | } |
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475 | |
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476 | #ifdef SHOW_MORE_INIT_SETTINGS |
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477 | printk("MSR %x \n", _read_MSR()); |
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478 | printk("Exit from bspstart\n"); |
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479 | #endif |
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480 | |
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481 | } |
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