1 | /* |
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2 | * This routine starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before this routine is invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2007. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * Modified to support the MCP750. |
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15 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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16 | * |
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17 | * Modified to support the Synergy VGM & Motorola PowerPC boards |
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18 | * (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004, 2005 |
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19 | * |
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20 | * Modified to support the MVME5500 board. |
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21 | * Also, the settings of L1, L2, and L3 caches is not necessary here. |
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22 | * (C) by Brookhaven National Lab., S. Kate Feng <feng1@bnl.gov>, 2003-2009 |
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23 | */ |
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24 | |
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25 | #include <string.h> |
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26 | #include <stdlib.h> |
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27 | #include <ctype.h> |
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28 | |
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29 | #include <rtems/system.h> |
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30 | #include <rtems/powerpc/powerpc.h> |
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31 | |
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32 | #include <libcpu/spr.h> /* registers.h is included here */ |
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33 | #include <bsp.h> |
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34 | #include <bsp/uart.h> |
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35 | #include <bsp/pci.h> |
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36 | #include <libcpu/bat.h> |
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37 | #include <libcpu/pte121.h> |
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38 | #include <libcpu/cpuIdent.h> |
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39 | #include <bsp/vectors.h> |
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40 | #include <bsp/bspException.h> |
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41 | |
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42 | #include <rtems/bspIo.h> |
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43 | #include <rtems/counter.h> |
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44 | #include <rtems/sptables.h> |
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45 | |
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46 | /* |
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47 | #define SHOW_MORE_INIT_SETTINGS |
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48 | #define SHOW_LCR1_REGISTER |
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49 | #define SHOW_LCR2_REGISTER |
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50 | #define SHOW_LCR3_REGISTER |
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51 | #define CONF_VPD |
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52 | */ |
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53 | |
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54 | extern uint32_t probeMemoryEnd(void); /* from shared/startup/probeMemoryEnd.c */ |
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55 | |
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56 | BSP_output_char_function_type BSP_output_char = BSP_output_char_via_serial; |
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57 | BSP_polling_getchar_function_type BSP_poll_char = NULL; |
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58 | |
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59 | extern void _return_to_ppcbug(void); |
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60 | extern unsigned long __rtems_end[]; |
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61 | extern unsigned get_L1CR(void), get_L2CR(void), get_L3CR(void); |
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62 | extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *); |
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63 | extern void BSP_pgtbl_activate(Triv121PgTbl); |
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64 | extern int I2Cread_eeprom(unsigned char I2cBusAddr, uint32_t devA2A1A0, uint32_t AddrBytes, unsigned char *pBuff, uint32_t numBytes); |
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65 | extern void BSP_vme_config(void); |
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66 | |
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67 | extern unsigned char ReadConfVPD_buff(int offset); |
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68 | |
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69 | uint32_t bsp_clicks_per_usec; |
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70 | |
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71 | typedef struct CmdLineRec_ { |
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72 | unsigned long size; |
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73 | char buf[0]; |
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74 | } CmdLineRec, *CmdLine; |
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75 | |
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76 | |
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77 | #define mtspr(reg, val) \ |
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78 | __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) |
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79 | |
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80 | |
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81 | #define mfspr(reg) \ |
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82 | ( { unsigned val; \ |
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83 | __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ |
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84 | val; } ) |
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85 | |
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86 | /* |
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87 | * Copy Additional boot param passed by boot loader |
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88 | */ |
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89 | #define MAX_LOADER_ADD_PARM 80 |
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90 | char loaderParam[MAX_LOADER_ADD_PARM]; |
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91 | |
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92 | /* |
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93 | * Total memory using RESIDUAL DATA |
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94 | */ |
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95 | unsigned int BSP_mem_size; |
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96 | /* |
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97 | * PCI Bus Frequency |
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98 | */ |
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99 | unsigned int BSP_bus_frequency; |
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100 | /* |
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101 | * processor clock frequency |
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102 | */ |
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103 | unsigned int BSP_processor_frequency; |
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104 | /* |
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105 | * Time base divisior (how many tick for 1 second). |
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106 | */ |
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107 | unsigned int BSP_time_base_divisor; |
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108 | static unsigned char ConfVPD_buff[200]; |
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109 | |
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110 | #define CMDLINE_BUF_SIZE 2048 |
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111 | |
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112 | static char cmdline_buf[CMDLINE_BUF_SIZE]; |
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113 | char *BSP_commandline_string = cmdline_buf; |
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114 | |
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115 | void BSP_panic(char *s) |
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116 | { |
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117 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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118 | __asm__ __volatile ("sc"); |
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119 | } |
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120 | |
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121 | void _BSP_Fatal_error(unsigned int v) |
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122 | { |
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123 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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124 | __asm__ __volatile ("sc"); |
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125 | } |
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126 | |
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127 | /* NOTE: we cannot simply malloc the commandline string; |
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128 | * save_boot_params() is called during a very early stage when |
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129 | * libc/malloc etc. are not yet initialized! |
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130 | * |
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131 | * Here's what we do: |
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132 | * |
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133 | * initial layout setup by the loader (preload.S): |
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134 | * |
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135 | * 0..RTEMS...__rtems_end | cmdline ....... TOP |
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136 | * |
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137 | * After the save_boot_params() routine returns, the stack area will be |
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138 | * set up (start.S): |
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139 | * |
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140 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ..... TOP |
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141 | * |
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142 | * initialize_executive_early() [called from boot_card()] |
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143 | * will initialize the workspace: |
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144 | * |
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145 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ...... | workspace | TOP |
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146 | * |
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147 | * and later calls our pretasking_hook() which ends up initializing |
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148 | * libc which in turn initializes the heap |
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149 | * |
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150 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | heap | workspace | TOP |
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151 | * |
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152 | * The idea here is to first move the commandline to the future 'heap' area |
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153 | * from where it will be picked up by our pretasking_hook(). |
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154 | * pretasking_hook() then moves it either to INIT_STACK or the workspace |
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155 | * area using proper allocation, initializes libc and finally moves |
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156 | * the data to the environment / malloced areas... |
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157 | */ |
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158 | |
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159 | /* this routine is called early at shared/start/start.S |
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160 | * and must be safe with a not properly aligned stack |
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161 | */ |
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162 | char * |
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163 | save_boot_params( |
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164 | void *r3, |
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165 | void *r4, |
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166 | void* r5, |
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167 | char *cmdline_start, |
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168 | char *cmdline_end |
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169 | ) |
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170 | { |
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171 | int i=cmdline_end-cmdline_start; |
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172 | |
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173 | if ( i >= CMDLINE_BUF_SIZE ) |
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174 | i = CMDLINE_BUF_SIZE-1; |
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175 | else if ( i < 0 ) |
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176 | i = 0; |
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177 | |
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178 | memmove(cmdline_buf, cmdline_start, i); |
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179 | cmdline_buf[i]=0; |
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180 | return cmdline_buf; |
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181 | } |
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182 | |
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183 | /* |
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184 | * bsp_start |
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185 | * |
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186 | * This routine does the bulk of the system initialization. |
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187 | */ |
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188 | |
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189 | void bsp_start( void ) |
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190 | { |
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191 | #ifdef CONF_VPD |
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192 | int i; |
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193 | #endif |
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194 | #ifdef SHOW_LCR1_REGISTER |
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195 | unsigned l1cr; |
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196 | #endif |
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197 | #ifdef SHOW_LCR2_REGISTER |
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198 | unsigned l2cr; |
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199 | #endif |
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200 | #ifdef SHOW_LCR3_REGISTER |
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201 | unsigned l3cr; |
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202 | #endif |
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203 | uintptr_t intrStackStart; |
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204 | uintptr_t intrStackSize; |
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205 | ppc_cpu_id_t myCpu; |
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206 | ppc_cpu_revision_t myCpuRevision; |
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207 | Triv121PgTbl pt=0; |
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208 | |
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209 | /* Till Straumann: 4/2005 |
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210 | * Need to map the system registers early, so we can printk... |
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211 | * (otherwise we silently die) |
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212 | */ |
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213 | /* |
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214 | * Kate Feng : PCI 0 domain memory space, want to leave room for the VME window |
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215 | */ |
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216 | setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE); |
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217 | |
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218 | /* Till Straumann: 2004 |
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219 | * map the PCI 0, 1 Domain I/O space, GT64260B registers |
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220 | * and the reserved area so that the size is the power of 2. |
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221 | * 2009 : map the entire 256 M space |
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222 | * |
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223 | */ |
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224 | setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE); |
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225 | |
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226 | |
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227 | /* |
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228 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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229 | * store the result in global variables so that it can be used latter... |
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230 | */ |
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231 | myCpu = get_ppc_cpu_type(); |
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232 | myCpuRevision = get_ppc_cpu_revision(); |
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233 | |
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234 | #ifdef SHOW_LCR1_REGISTER |
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235 | l1cr = get_L1CR(); |
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236 | printk("Initial L1CR value = %x\n", l1cr); |
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237 | #endif |
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238 | |
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239 | /* |
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240 | * Initialize the interrupt related settings. |
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241 | */ |
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242 | intrStackStart = (uintptr_t) __rtems_end; |
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243 | intrStackSize = rtems_configuration_get_interrupt_stack_size(); |
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244 | |
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245 | /* |
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246 | * Initialize default raw exception handlers. |
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247 | */ |
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248 | ppc_exc_initialize( |
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249 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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250 | intrStackStart, |
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251 | intrStackSize |
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252 | ); |
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253 | |
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254 | /* |
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255 | * Init MMU block address translation to enable hardware |
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256 | * access |
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257 | * More PCI1 memory mapping to be done after BSP_pgtbl_activate. |
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258 | */ |
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259 | printk("-----------------------------------------\n"); |
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260 | printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version ); |
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261 | printk("-----------------------------------------\n"); |
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262 | |
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263 | BSP_mem_size = probeMemoryEnd(); |
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264 | |
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265 | /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit |
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266 | * of System Status register |
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267 | */ |
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268 | /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */ |
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269 | BSP_bus_frequency = 133333333; |
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270 | BSP_processor_frequency = 1000000000; |
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271 | /* P94 : 7455 clocks the TB/DECR at 1/4 of the system bus clock frequency */ |
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272 | BSP_time_base_divisor = 4000; |
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273 | |
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274 | /* Maybe not setup yet becuase of the warning message */ |
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275 | /* Allocate and set up the page table mappings |
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276 | * This is only available on >604 CPUs. |
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277 | * |
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278 | * NOTE: This setup routine may modify the available memory |
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279 | * size. It is essential to call it before |
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280 | * calculating the workspace etc. |
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281 | */ |
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282 | pt = BSP_pgtbl_setup(&BSP_mem_size); |
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283 | if (!pt) |
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284 | printk("WARNING: unable to setup page tables.\n"); |
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285 | |
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286 | printk("Now BSP_mem_size = 0x%x\n",BSP_mem_size); |
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287 | |
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288 | /* P94 : 7455 TB/DECR is clocked by the system bus clock frequency */ |
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289 | |
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290 | bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); |
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291 | rtems_counter_initialize_converter( |
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292 | BSP_bus_frequency / (BSP_time_base_divisor / 1000) |
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293 | ); |
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294 | |
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295 | /* |
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296 | * Initalize RTEMS IRQ system |
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297 | */ |
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298 | BSP_rtems_irq_mng_init(0); |
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299 | |
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300 | #ifdef SHOW_LCR2_REGISTER |
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301 | l2cr = get_L2CR(); |
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302 | printk("Initial L2CR value = %x\n", l2cr); |
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303 | #endif |
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304 | |
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305 | #ifdef SHOW_LCR3_REGISTER |
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306 | /* L3CR needs DEC int. handler installed for bsp_delay()*/ |
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307 | l3cr = get_L3CR(); |
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308 | printk("Initial L3CR value = %x\n", l3cr); |
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309 | #endif |
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310 | |
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311 | |
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312 | /* Activate the page table mappings only after |
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313 | * initializing interrupts because the irq_mng_init() |
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314 | * routine needs to modify the text |
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315 | */ |
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316 | if (pt) { |
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317 | #ifdef SHOW_MORE_INIT_SETTINGS |
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318 | printk("Page table setup finished; will activate it NOW...\n"); |
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319 | #endif |
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320 | BSP_pgtbl_activate(pt); |
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321 | } |
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322 | /* Read Configuration Vital Product Data (VPD) */ |
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323 | if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150)) |
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324 | printk("I2Cread_eeprom() error \n"); |
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325 | else { |
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326 | #ifdef CONF_VPD |
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327 | printk("\n"); |
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328 | for (i=0; i<150; i++) { |
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329 | printk("%2x ", ConfVPD_buff[i]); |
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330 | if ((i % 20)==0 ) printk("\n"); |
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331 | } |
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332 | printk("\n"); |
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333 | #endif |
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334 | } |
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335 | |
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336 | /* |
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337 | * PCI 1 domain memory space |
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338 | */ |
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339 | setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE); |
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340 | |
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341 | |
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342 | #ifdef SHOW_MORE_INIT_SETTINGS |
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343 | printk("Going to start PCI buses scanning and initialization\n"); |
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344 | #endif |
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345 | pci_initialize(); |
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346 | #ifdef SHOW_MORE_INIT_SETTINGS |
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347 | printk("Number of PCI buses found is : %d\n", pci_bus_count()); |
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348 | #endif |
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349 | |
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350 | /* Install our own exception handler (needs PCI) */ |
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351 | globalExceptHdl = BSP_exceptionHandler; |
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352 | |
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353 | /* clear hostbridge errors. MCP signal is not used on the MVME5500 |
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354 | * PCI config space scanning code will trip otherwise :-( |
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355 | */ |
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356 | _BSP_clear_hostbridge_errors(0, 1 /*quiet*/); |
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357 | |
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358 | #ifdef SHOW_MORE_INIT_SETTINGS |
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359 | printk("MSR %x \n", _read_MSR()); |
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360 | printk("Exit from bspstart\n"); |
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361 | #endif |
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362 | |
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363 | } |
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364 | |
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365 | unsigned char ReadConfVPD_buff(int offset) |
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366 | { |
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367 | return(ConfVPD_buff[offset]); |
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368 | } |
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