[7be6ad9] | 1 | /* |
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| 2 | * This routine starts the application. It includes application, |
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| 3 | * board, and monitor specific initialization and configuration. |
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| 4 | * The generic CPU dependent initialization has been performed |
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| 5 | * before this routine is invoked. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-1998. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[f8e0327] | 12 | * http://www.rtems.com/license/LICENSE. |
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[7be6ad9] | 13 | * |
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| 14 | * Modified to support the MCP750. |
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| 15 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 16 | * |
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| 17 | * Modified to support the Synergy VGM & Motorola PowerPC boards. |
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| 18 | * Many thanks to Till Straumann for providing assistance to port the |
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| 19 | * BSP_pgtbl_xxx(). |
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| 20 | * (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004 |
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| 21 | * |
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| 22 | * Modified to support the MVME5500 board |
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| 23 | * (C) by S. Kate Feng <feng1@bnl.gov>, 2003, 2004 |
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| 24 | * |
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[f8e0327] | 25 | * $Id$ |
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[7be6ad9] | 26 | */ |
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[f8e0327] | 27 | |
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[7be6ad9] | 28 | #include <string.h> |
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| 29 | #include <stdlib.h> |
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| 30 | #include <ctype.h> |
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| 31 | |
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| 32 | #include <rtems/system.h> |
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| 33 | #include <rtems/libio.h> |
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| 34 | #include <rtems/libcsupport.h> |
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| 35 | /*#include <bsp/consoleIo.h>*/ |
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| 36 | #include <libcpu/spr.h> /* registers.h is included here */ |
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| 37 | #include <bsp.h> |
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| 38 | #include <bsp/uart.h> |
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| 39 | #include <bsp/pci.h> |
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| 40 | #include <libcpu/bat.h> |
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| 41 | #include <libcpu/pte121.h> |
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| 42 | #include <libcpu/cpuIdent.h> |
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| 43 | #include <bsp/vectors.h> |
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| 44 | #include <bsp/bspException.h> |
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| 45 | |
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| 46 | /* for RTEMS_VERSION :-( I dont like the preassembled string */ |
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| 47 | #include <rtems/sptables.h> |
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| 48 | |
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| 49 | #ifdef __RTEMS_APPLICATION__ |
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| 50 | #undef __RTEMS_APPLICATION__ |
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| 51 | #endif |
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| 52 | |
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| 53 | /* |
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| 54 | #define SHOW_MORE_INIT_SETTINGS |
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| 55 | #define SHOW_LCR1_REGISTER |
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| 56 | #define SHOW_LCR2_REGISTER |
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| 57 | #define SHOW_LCR3_REGISTER |
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| 58 | #define CONF_VPD |
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| 59 | */ |
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| 60 | |
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| 61 | /* there is no public Workspace_Free() variant :-( */ |
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| 62 | #include <rtems/score/wkspace.h> |
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| 63 | |
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[f4a59e33] | 64 | uint32_t |
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| 65 | _bsp_sbrk_init(uint32_t heap_start, uint32_t *heap_size_p); |
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[7be6ad9] | 66 | |
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| 67 | /* provide access to the command line parameters */ |
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| 68 | char *BSP_commandline_string = 0; |
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| 69 | |
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| 70 | BSP_output_char_function_type BSP_output_char = BSP_output_char_via_serial; |
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| 71 | |
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| 72 | extern void _return_to_ppcbug(); |
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| 73 | extern unsigned long __rtems_end[]; |
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| 74 | extern void L1_caches_enables(); |
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| 75 | extern unsigned get_L1CR(), get_L2CR(), get_L3CR(); |
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| 76 | extern unsigned set_L2CR(unsigned); |
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| 77 | extern void bsp_cleanup(void); |
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| 78 | extern Triv121PgTbl BSP_pgtbl_setup(); |
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| 79 | extern void BSP_pgtbl_activate(); |
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| 80 | extern int I2Cread_eeprom(); |
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| 81 | extern void BSP_vme_config(void); |
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| 82 | |
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| 83 | SPR_RW(SPRG0) |
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| 84 | SPR_RW(SPRG1) |
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| 85 | |
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| 86 | typedef struct CmdLineRec_ { |
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| 87 | unsigned long size; |
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| 88 | char buf[0]; |
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| 89 | } CmdLineRec, *CmdLine; |
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| 90 | |
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| 91 | |
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| 92 | #define mtspr(reg, val) \ |
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| 93 | __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) |
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| 94 | |
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| 95 | |
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| 96 | #define mfspr(reg) \ |
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| 97 | ( { unsigned val; \ |
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| 98 | __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ |
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| 99 | val; } ) |
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| 100 | |
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| 101 | /* |
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| 102 | * Copy Additional boot param passed by boot loader |
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| 103 | */ |
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| 104 | #define MAX_LOADER_ADD_PARM 80 |
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| 105 | char loaderParam[MAX_LOADER_ADD_PARM]; |
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| 106 | |
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| 107 | /* |
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| 108 | * Total memory using RESIDUAL DATA |
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| 109 | */ |
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| 110 | unsigned int BSP_mem_size; |
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| 111 | /* |
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| 112 | * PCI Bus Frequency |
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| 113 | */ |
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| 114 | unsigned int BSP_bus_frequency; |
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| 115 | /* |
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| 116 | * processor clock frequency |
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| 117 | */ |
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| 118 | unsigned int BSP_processor_frequency; |
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| 119 | /* |
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| 120 | * Time base divisior (how many tick for 1 second). |
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| 121 | */ |
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| 122 | unsigned int BSP_time_base_divisor; |
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| 123 | unsigned char ConfVPD_buff[200]; |
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| 124 | |
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| 125 | /* |
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| 126 | * system init stack and soft ir stack size |
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| 127 | */ |
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| 128 | #define INIT_STACK_SIZE 0x1000 |
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| 129 | #define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY |
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| 130 | |
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| 131 | /* calculate the heap start */ |
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| 132 | static unsigned long |
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| 133 | heapStart(void) |
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| 134 | { |
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| 135 | unsigned long rval; |
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[f4a59e33] | 136 | rval = ((uint32_t) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE; |
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[7be6ad9] | 137 | if (rval & (CPU_ALIGNMENT-1)) |
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| 138 | rval = (rval + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); |
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| 139 | return rval; |
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| 140 | } |
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| 141 | |
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| 142 | void BSP_panic(char *s) |
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| 143 | { |
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| 144 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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| 145 | __asm__ __volatile ("sc"); |
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| 146 | } |
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| 147 | |
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| 148 | void _BSP_Fatal_error(unsigned int v) |
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| 149 | { |
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| 150 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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| 151 | __asm__ __volatile ("sc"); |
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| 152 | } |
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| 153 | |
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| 154 | /* |
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| 155 | * The original table from the application and our copy of it with |
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| 156 | * some changes. |
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| 157 | */ |
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| 158 | |
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| 159 | extern rtems_configuration_table Configuration; |
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| 160 | |
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| 161 | rtems_configuration_table BSP_Configuration; |
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| 162 | |
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| 163 | rtems_cpu_table Cpu_table; |
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| 164 | |
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| 165 | char *rtems_progname; |
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| 166 | |
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| 167 | /* |
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| 168 | * Use the shared implementations of the following routines |
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| 169 | */ |
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| 170 | |
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| 171 | extern void bsp_postdriver_hook(void); /* see c/src/lib/libbsp/shared/bsppost.c */ |
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| 172 | |
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[b3a78e34] | 173 | extern void bsp_libc_init( void *, uint32_t, int ); |
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[7be6ad9] | 174 | |
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| 175 | /* |
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| 176 | * Function: bsp_pretasking_hook |
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| 177 | * Created: 95/03/10 |
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| 178 | * |
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| 179 | * Description: |
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| 180 | * BSP pretasking hook. Called just before drivers are initialized. |
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| 181 | * Used to setup libc and install any BSP extensions. |
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| 182 | * |
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| 183 | * NOTES: |
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| 184 | * Must not use libc (to do io) from here, since drivers are |
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| 185 | * not yet initialized. |
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| 186 | * |
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| 187 | */ |
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| 188 | |
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| 189 | void bsp_pretasking_hook(void) |
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| 190 | { |
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[f4a59e33] | 191 | uint32_t heap_start=heapStart(); |
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| 192 | uint32_t heap_size,heap_sbrk_spared; |
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| 193 | extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*); |
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[7be6ad9] | 194 | |
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| 195 | heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size; |
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| 196 | |
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| 197 | heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size); |
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| 198 | |
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| 199 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 200 | printk(" HEAP start %x size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared); |
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| 201 | #endif |
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| 202 | |
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| 203 | bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); |
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| 204 | |
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| 205 | #ifdef RTEMS_DEBUG |
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| 206 | rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); |
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| 207 | #endif |
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| 208 | } |
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| 209 | |
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| 210 | void zero_bss() |
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| 211 | { |
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| 212 | /* prevent these from being accessed in the short data areas */ |
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| 213 | extern unsigned long __bss_start[], __sbss_start[], __sbss_end[]; |
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| 214 | extern unsigned long __sbss2_start[], __sbss2_end[]; |
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| 215 | memset(__sbss_start, 0, ((unsigned) __sbss_end) - ((unsigned)__sbss_start)); |
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| 216 | memset(__sbss2_start, 0, ((unsigned) __sbss2_end) - ((unsigned)__sbss2_start)); |
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| 217 | memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start)); |
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| 218 | } |
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| 219 | |
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| 220 | /* NOTE: we cannot simply malloc the commandline string; |
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| 221 | * save_boot_params() is called during a very early stage when |
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| 222 | * libc/malloc etc. are not yet initialized! |
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| 223 | * |
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| 224 | * Here's what we do: |
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| 225 | * |
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| 226 | * initial layout setup by the loader (preload.S): |
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| 227 | * |
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| 228 | * 0..RTEMS...__rtems_end | cmdline ....... TOP |
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| 229 | * |
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| 230 | * After the save_boot_params() routine returns, the stack area will be |
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| 231 | * set up (start.S): |
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| 232 | * |
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| 233 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ..... TOP |
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| 234 | * |
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| 235 | * initialize_executive_early() [called from boot_card()] |
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| 236 | * will initialize the workspace: |
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| 237 | * |
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| 238 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | ...... | workspace | TOP |
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| 239 | * |
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| 240 | * and later calls our pretasking_hook() which ends up initializing |
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| 241 | * libc which in turn initializes the heap |
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| 242 | * |
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| 243 | * 0..RTEMS..__rtems_end | INIT_STACK | IRQ_STACK | heap | workspace | TOP |
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| 244 | * |
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| 245 | * The idea here is to first move the commandline to the future 'heap' area |
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| 246 | * from where it will be picked up by our pretasking_hook(). |
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| 247 | * pretasking_hook() then moves it either to INIT_STACK or the workspace |
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| 248 | * area using proper allocation, initializes libc and finally moves |
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| 249 | * the data to the environment / malloced areas... |
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| 250 | */ |
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| 251 | |
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| 252 | /* this routine is called early at shared/start/start.S |
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| 253 | * and must be safe with a not properly aligned stack |
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| 254 | */ |
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| 255 | void |
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| 256 | save_boot_params(void *r3, void *r4, void* r5, char *cmdline_start, char *cmdline_end) |
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| 257 | { |
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| 258 | int i=cmdline_end-cmdline_start; |
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| 259 | CmdLine future_heap=(CmdLine)heapStart(); |
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| 260 | |
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| 261 | /* get the string out of the stack area into the future heap region; |
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| 262 | * assume there's enough memory... |
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| 263 | */ |
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| 264 | memmove(future_heap->buf,cmdline_start,i); |
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| 265 | /* make sure there's an end of string marker */ |
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| 266 | future_heap->buf[i++]=0; |
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| 267 | future_heap->size=i; |
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| 268 | } |
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| 269 | |
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| 270 | |
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| 271 | /* Configure and enable the L3CR */ |
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| 272 | void config_enable_L3CR(unsigned l3cr) |
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| 273 | { |
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| 274 | unsigned x; |
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| 275 | |
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| 276 | /* By The Book (numbered steps from section 3.7.3.1 of MPC7450UM) */ |
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| 277 | /* |
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| 278 | * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and |
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| 279 | * L3CLKEN. (also mask off reserved bits in case they were included |
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| 280 | * in L3CR_CONFIG) |
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| 281 | */ |
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| 282 | l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_LOCK_745x|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); |
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| 283 | mtspr(L3CR, l3cr); |
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| 284 | |
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| 285 | /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ |
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| 286 | l3cr |= 0x04000000; |
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| 287 | mtspr(L3CR, l3cr); |
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| 288 | |
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| 289 | /* 3: Set L3CLKEN to 1*/ |
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| 290 | l3cr |= L3CR_L3CLKEN; |
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| 291 | mtspr(L3CR, l3cr); |
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| 292 | |
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| 293 | /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ |
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| 294 | __asm __volatile("dssall;sync"); |
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| 295 | /* L3 cache is already disabled, no need to clear L3E */ |
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| 296 | mtspr(L3CR, l3cr|L3CR_L3I); |
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| 297 | |
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| 298 | do { |
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| 299 | x = mfspr(L3CR); |
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| 300 | } while (x & L3CR_L3I); |
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| 301 | |
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| 302 | /* 6: Clear L3CLKEN to 0 */ |
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| 303 | l3cr &= ~L3CR_L3CLKEN; |
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| 304 | mtspr(L3CR, l3cr); |
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| 305 | |
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| 306 | /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ |
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| 307 | __asm __volatile("sync"); |
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| 308 | rtems_bsp_delay_in_bus_cycles(100); |
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| 309 | |
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| 310 | /* 8: Set L3E and L3CLKEN */ |
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| 311 | l3cr |= (L3CR_L3E|L3CR_L3CLKEN); |
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| 312 | mtspr(L3CR, l3cr); |
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| 313 | |
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| 314 | /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ |
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| 315 | __asm __volatile("sync"); |
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| 316 | |
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| 317 | rtems_bsp_delay_in_bus_cycles(100); |
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| 318 | } |
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| 319 | |
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| 320 | /* |
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| 321 | * bsp_start |
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| 322 | * |
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| 323 | * This routine does the bulk of the system initialization. |
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| 324 | */ |
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| 325 | |
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| 326 | void bsp_start( void ) |
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| 327 | { |
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[05682dc] | 328 | #ifdef CONF_VPD |
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[7be6ad9] | 329 | int i; |
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[05682dc] | 330 | #endif |
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[7be6ad9] | 331 | unsigned char *stack; |
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| 332 | unsigned long *r1sp; |
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[05682dc] | 333 | #ifdef SHOW_LCR1_REGISTER |
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| 334 | unsigned l1cr; |
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| 335 | #endif |
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| 336 | #ifdef SHOW_LCR2_REGISTER |
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| 337 | unsigned l2cr; |
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| 338 | #endif |
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| 339 | #ifdef SHOW_LCR3_REGISTER |
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| 340 | unsigned l3cr; |
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| 341 | #endif |
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[7be6ad9] | 342 | register unsigned char* intrStack; |
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| 343 | unsigned char *work_space_start; |
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| 344 | ppc_cpu_id_t myCpu; |
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| 345 | ppc_cpu_revision_t myCpuRevision; |
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| 346 | Triv121PgTbl pt=0; |
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| 347 | /* |
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| 348 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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| 349 | * store the result in global variables so that it can be used latter... |
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| 350 | */ |
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| 351 | myCpu = get_ppc_cpu_type(); |
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| 352 | myCpuRevision = get_ppc_cpu_revision(); |
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| 353 | |
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| 354 | /* |
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| 355 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
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| 356 | * relevant CPU type so that the reason why there is no use of myCpu... |
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| 357 | * |
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| 358 | * MOTLoad default is good. Otherwise, one would have to disable L2, L3 |
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| 359 | * first before settting L1. Then L1->L2->L3. |
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| 360 | * |
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| 361 | L1_caches_enables();*/ |
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| 362 | |
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| 363 | #ifdef SHOW_LCR1_REGISTER |
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| 364 | l1cr = get_L1CR(); |
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| 365 | printk("Initial L1CR value = %x\n", l1cr); |
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| 366 | #endif |
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| 367 | |
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| 368 | /* |
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| 369 | * the initial stack has aready been set to this value in start.S |
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| 370 | * so there is no need to set it in r1 again... It is just for info |
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| 371 | * so that it can be printed without accessing R1. |
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| 372 | */ |
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| 373 | stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; |
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| 374 | |
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| 375 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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[b3a78e34] | 376 | *((uint32_t *)stack) = 0; |
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[7be6ad9] | 377 | |
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| 378 | /* fill stack with pattern for debugging */ |
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| 379 | __asm__ __volatile__("mr %0, %%r1":"=r"(r1sp)); |
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| 380 | while (--r1sp >= (unsigned long*)__rtems_end) |
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| 381 | *r1sp=0xeeeeeeee; |
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| 382 | |
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| 383 | /* |
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| 384 | * Initialize the interrupt related settings |
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| 385 | * SPRG0 = interrupt nesting level count |
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| 386 | * SPRG1 = software managed IRQ stack |
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| 387 | * |
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| 388 | * This could be done latter (e.g in IRQ_INIT) but it helps to understand |
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| 389 | * some settings below... |
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| 390 | */ |
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| 391 | intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; |
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| 392 | |
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| 393 | /* make sure it's properly aligned */ |
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[b3a78e34] | 394 | (uint32_t)intrStack &= ~(CPU_STACK_ALIGNMENT-1); |
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[7be6ad9] | 395 | |
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| 396 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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[b3a78e34] | 397 | *((uint32_t *)intrStack) = 0; |
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[7be6ad9] | 398 | |
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| 399 | _write_SPRG1((unsigned int)intrStack); |
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| 400 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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| 401 | |
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| 402 | /* |
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| 403 | * Initialize default raw exception hanlders. See vectors/vectors_init.c |
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| 404 | */ |
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| 405 | initialize_exceptions(); |
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| 406 | /* |
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| 407 | * Init MMU block address translation to enable hardware |
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| 408 | * access |
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| 409 | * More PCI1 memory mapping to be done after BSP_pgtbl_activate. |
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| 410 | */ |
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| 411 | /* |
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| 412 | * PCI 0 domain memory space, want to leave room for the VME window |
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| 413 | */ |
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| 414 | setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE); |
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| 415 | |
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| 416 | /* map the PCI 0, 1 Domain I/O space, GT64260B registers |
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| 417 | * and the reserved area so that the size is the power of 2. |
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| 418 | */ |
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| 419 | setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE); |
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| 420 | |
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| 421 | printk("-----------------------------------------\n"); |
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| 422 | printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version ); |
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| 423 | printk("-----------------------------------------\n"); |
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| 424 | |
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| 425 | #ifdef TEST_RETURN_TO_PPCBUG |
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| 426 | printk("Hit <Enter> to return to PPCBUG monitor\n"); |
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| 427 | printk("When Finished hit GO. It should print <Back from monitor>\n"); |
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| 428 | debug_getc(); |
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| 429 | _return_to_ppcbug(); |
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| 430 | printk("Back from monitor\n"); |
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| 431 | _return_to_ppcbug(); |
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| 432 | #endif /* TEST_RETURN_TO_PPCBUG */ |
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| 433 | |
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| 434 | #ifdef TEST_RAW_EXCEPTION_CODE |
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| 435 | printk("Testing exception handling Part 1\n"); |
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| 436 | /* |
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| 437 | * Cause a software exception |
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| 438 | */ |
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| 439 | __asm__ __volatile ("sc"); |
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| 440 | /* |
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| 441 | * Check we can still catch exceptions and returned coorectly. |
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| 442 | */ |
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| 443 | printk("Testing exception handling Part 2\n"); |
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| 444 | __asm__ __volatile ("sc"); |
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| 445 | #endif |
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| 446 | |
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| 447 | BSP_mem_size = _512M; |
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| 448 | /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit of System Status register */ |
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| 449 | /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */ |
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| 450 | BSP_bus_frequency = 133333333; |
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| 451 | BSP_processor_frequency = 1000000000; |
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| 452 | BSP_time_base_divisor = 4000;/* P94 : 7455 clocks the TB/DECR at 1/4 of the system bus clock frequency */ |
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| 453 | |
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| 454 | |
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| 455 | /* Maybe not setup yet becuase of the warning message */ |
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| 456 | /* Allocate and set up the page table mappings |
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| 457 | * This is only available on >604 CPUs. |
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| 458 | * |
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| 459 | * NOTE: This setup routine may modify the available memory |
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| 460 | * size. It is essential to call it before |
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| 461 | * calculating the workspace etc. |
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| 462 | */ |
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| 463 | pt = BSP_pgtbl_setup(&BSP_mem_size); |
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| 464 | if (!pt) |
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| 465 | printk("WARNING: unable to setup page tables.\n"); |
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| 466 | |
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| 467 | printk("Now BSP_mem_size = 0x%x\n",BSP_mem_size); |
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| 468 | |
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| 469 | /* |
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| 470 | * Set up our hooks |
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| 471 | * Make sure libc_init is done before drivers initialized so that |
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| 472 | * they can use atexit() |
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| 473 | */ |
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| 474 | |
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| 475 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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| 476 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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| 477 | Cpu_table.do_zero_of_workspace = TRUE; |
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| 478 | Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; |
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| 479 | /* P94 : 7455 TB/DECR is clocked by the system bus clock frequency */ |
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| 480 | Cpu_table.clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); |
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| 481 | Cpu_table.exceptions_in_RAM = TRUE; |
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| 482 | _CPU_Table = Cpu_table;/* <skf> for rtems_bsp_delay() */ |
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| 483 | |
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| 484 | printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size); |
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| 485 | work_space_start = |
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| 486 | (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size; |
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| 487 | |
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| 488 | if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) { |
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| 489 | printk( "bspstart: Not enough RAM!!!\n" ); |
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| 490 | bsp_cleanup(); |
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| 491 | } |
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| 492 | |
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| 493 | BSP_Configuration.work_space_start = work_space_start; |
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| 494 | |
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| 495 | /* |
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| 496 | * Initalize RTEMS IRQ system |
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| 497 | */ |
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| 498 | BSP_rtems_irq_mng_init(0); |
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| 499 | |
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| 500 | /* |
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| 501 | * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for |
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| 502 | * relevant CPU type (mpc750)... |
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| 503 | * |
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| 504 | * It also takes care of flushing the cache under certain conditions: |
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| 505 | * current going to (E==enable, I==invalidate) |
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| 506 | * E E | I -> __NOT_FLUSHED_, invalidated, stays E |
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| 507 | * E I -> flush & disable, invalidate |
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| 508 | * E E -> nothing, stays E |
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| 509 | * 0 E | I -> not flushed, invalidated, enabled |
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| 510 | * 0 | I -> not flushed, invalidated, stays off |
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| 511 | * 0 E -> not flushed, _NO_INVALIDATE, enabled |
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| 512 | * |
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| 513 | * The first and the last combinations are potentially dangerous! |
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| 514 | * |
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| 515 | * NOTE: we assume the essential cache parameters (speed, size etc.) |
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| 516 | * have been set correctly by the firmware! |
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| 517 | * |
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| 518 | */ |
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| 519 | #ifdef SHOW_LCR2_REGISTER |
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| 520 | l2cr = get_L2CR(); |
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| 521 | printk("Initial L2CR value = %x\n", l2cr); |
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| 522 | #endif |
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| 523 | #if 0 |
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| 524 | /* Again, MOTload setup seems to be fine. Otherwise, one would |
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| 525 | * have to disable the L3 cahce, then R2 ->R3 |
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| 526 | */ |
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| 527 | if ( -1 != (int)l2cr ) { |
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| 528 | /* -1 would mean that this machine doesn't support L2 */ |
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| 529 | |
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| 530 | l2cr &= ~( L2CR_LOCK_745x); /* clear 'data only' and 'instruction only' */ |
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| 531 | l2cr |= L2CR_L3OH0; /* L3 output hold 0 should be set */ |
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| 532 | if ( ! (l2cr & L2CR_L2E) ) { |
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| 533 | /* we are going to enable the L2 - hence we |
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| 534 | * MUST invalidate it first; however, if |
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| 535 | * it was enabled already, we MUST NOT |
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| 536 | * invalidate it!! |
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| 537 | */ |
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| 538 | l2cr |= L2CR_L2E | L2CR_L2I; |
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| 539 | l2cr=set_L2CR(l2cr); |
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| 540 | } |
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| 541 | l2cr=set_L2CR(l2cr); |
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| 542 | } |
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| 543 | #endif |
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| 544 | |
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| 545 | #ifdef SHOW_LCR3_REGISTER |
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| 546 | /* L3CR needs DEC int. handler installed for bsp_delay()*/ |
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| 547 | l3cr = get_L3CR(); |
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| 548 | printk("Initial L3CR value = %x\n", l3cr); |
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| 549 | #endif |
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| 550 | |
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| 551 | #if 0 |
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| 552 | /* Again, use the MOTLoad default for L3CR again */ |
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| 553 | if ( -1 != (int)l3cr ) { |
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| 554 | /* -1 would mean that this machine doesn't support L3 */ |
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| 555 | /* BSD : %2 , SDRAM late wirte |
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| 556 | l3cr |= L3SIZ_2M|L3CLK_20|L3RT_PIPELINE_LATE; */ |
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| 557 | /* MOTLOad :0xDF826000-> %5, 4 clocks sample point,3 p-clocks SP */ |
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| 558 | l3cr |= L3CR_L3PE| L3SIZ_2M|L3CLK_50|L3CKSP_4|L3PSP_3; |
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| 559 | |
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| 560 | /* TOCHECK MOTload had L2 cache enabled, try to set nothing first */ |
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| 561 | if ( !(l3cr & L3CR_L3E)) { |
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| 562 | l3cr |= L3CR_L3E | L3CR_L3I; |
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| 563 | config_enable_L3CR(l3cr); |
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| 564 | } |
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| 565 | } |
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| 566 | #endif |
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| 567 | |
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| 568 | /* Activate the page table mappings only after |
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| 569 | * initializing interrupts because the irq_mng_init() |
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| 570 | * routine needs to modify the text |
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| 571 | */ |
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| 572 | if (pt) { |
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| 573 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 574 | printk("Page table setup finished; will activate it NOW...\n"); |
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| 575 | #endif |
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| 576 | BSP_pgtbl_activate(pt); |
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| 577 | } |
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| 578 | |
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| 579 | /* |
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| 580 | * PCI 1 domain memory space |
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| 581 | */ |
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| 582 | setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE); |
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| 583 | |
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| 584 | |
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| 585 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 586 | printk("Going to start PCI buses scanning and initialization\n"); |
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| 587 | #endif |
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| 588 | InitializePCI(); |
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| 589 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 590 | printk("Number of PCI buses found is : %d\n", BusCountPCI()); |
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| 591 | #endif |
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| 592 | |
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| 593 | /* Install our own exception handler (needs PCI) */ |
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| 594 | globalExceptHdl = BSP_exceptionHandler; |
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| 595 | |
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| 596 | /* clear hostbridge errors. MCP signal is not used on the MVME5500 |
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| 597 | * PCI config space scanning code will trip otherwise :-( |
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| 598 | */ |
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| 599 | _BSP_clear_hostbridge_errors(0, 1 /*quiet*/); |
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| 600 | |
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| 601 | /* |
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| 602 | * Initialize VME bridge - needs working PCI |
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| 603 | * and IRQ subsystems... |
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| 604 | */ |
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| 605 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 606 | printk("Going to initialize VME bridge\n"); |
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| 607 | #endif |
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| 608 | /* VME initialization is in a separate file so apps which don't use |
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| 609 | * VME or want a different configuration may link against a customized |
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| 610 | * routine. |
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| 611 | */ |
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| 612 | BSP_vme_config(); |
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| 613 | |
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| 614 | /* Read Configuration Vital Product Data (VPD) */ |
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| 615 | if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150)) |
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| 616 | printk("I2Cread_eeprom() error \n"); |
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| 617 | else { |
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| 618 | #ifdef CONF_VPD |
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| 619 | printk("\n"); |
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| 620 | for (i=0; i<150; i++) { |
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| 621 | printk("%2x ", ConfVPD_buff[i]); |
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| 622 | if ((i % 20)==0 ) printk("\n"); |
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| 623 | } |
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| 624 | printk("\n"); |
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| 625 | #endif |
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| 626 | } |
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| 627 | |
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| 628 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 629 | printk("MSR %x \n", _read_MSR()); |
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| 630 | printk("Exit from bspstart\n"); |
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| 631 | #endif |
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| 632 | |
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| 633 | } |
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