source: rtems/c/src/lib/libbsp/powerpc/mvme5500/start/start.S @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 *  start.S :     RTEMS entry point
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  S. Kate Feng <feng1@bnl.gov>, April 2004
7 *  Mapped the 2nd 256MB of RAM to support the MVME5500/MVME6100 boards
8 *     
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 */
14
15#include <rtems/asm.h>
16#include <rtems/score/cpu.h>
17#include <rtems/powerpc/powerpc.h>
18
19#include <libcpu/io.h>
20#include <libcpu/bat.h>
21#include <bspopts.h>
22
23#define SYNC \
24        sync; \
25        isync
26
27#define KERNELBASE      0x0
28#define MEM256MB        0x10000000
29
30#define MONITOR_ENTER                   \
31        mfmsr   r10             ;       \
32        ori     r10,r10,MSR_IP  ;       \
33        mtmsr   r10             ;       \
34        li      r10,0x63        ;       \
35        sc
36
37        .text
38        .globl  __rtems_entry_point
39        .type   __rtems_entry_point,@function
40__rtems_entry_point:
41#ifdef DEBUG_EARLY_START
42        MONITOR_ENTER
43#endif
44
45/*
46 * PREP
47 * This is jumped to on prep systems right after the kernel is relocated
48 * to its proper place in memory by the boot loader.  The expected layout
49 * of the regs is:
50 *   r3: ptr to residual data
51 *   r4: initrd_start or if no initrd then 0
52 *   r5: initrd_end - unused if r4 is 0
53 *   r6: Start of command line string
54 *   r7: End of command line string
55 *
56 *   The Prep boot loader insure that the MMU is currently off...
57 *
58 */
59
60        mr      r31,r3                  /* save parameters */
61        mr      r30,r4
62        mr      r29,r5
63        mr      r28,r6
64        mr      r27,r7
65
66#ifdef __ALTIVEC__
67        /* enable altivec; gcc may use it! */
68        mfmsr r0
69        oris  r0, r0, (1<<(31-16-6))
70        mtmsr r0
71        /*
72         * set vscr and vrsave to known values
73         */
74        li    r0, 0
75        mtvrsave r0
76        vxor   0,0,0
77        mtvscr 0
78#endif
79
80        /*
81         * Make sure we have nothing in BATS and TLB
82         */
83        bl      CPU_clear_bats_early
84        bl      flush_tlbs
85/*
86 * Use the first pair of BAT registers to map the 1st 256MB
87 * of RAM to KERNELBASE.
88 */
89        lis     r11,KERNELBASE@h
90/* set up BAT registers for 604 */
91        ori     r11,r11,0x1ffe
92        li      r8,2                    /* R/W access */
93        isync
94        mtspr   DBAT0L,r8               /* N.B. 6xx (not 601) have valid */
95        mtspr   DBAT0U,r11              /* bit in upper BAT register */
96        mtspr   IBAT0L,r8
97        mtspr   IBAT0U,r11
98        isync
99/*
100 * <skf> Use the 2nd pair of BAT registers to map the 2nd 256MB
101 * of RAM to 0x10000000.
102 */
103        lis     r11,MEM256MB@h
104        ori     r11,r11,0x1ffe          /* set up BAT1 registers for 604+ */
105        lis     r8,MEM256MB@h
106        ori     r8,r8,2
107        isync
108        mtspr   DBAT1L,r8               /* N.B. 6xx (not 601) have valid */
109        mtspr   DBAT1U,r11              /* bit in upper BAT register */
110        mtspr   IBAT1L,r8
111        mtspr   IBAT1U,r11
112        isync
113
114/*
115 * we now have the two 256M of ram mapped with the bats. We are still
116 * running on the bootloader stack and cannot switch to an RTEMS allocated
117 * init stack before copying the residual data that may have been set just
118 * after rtems_end address. This bug has been experienced on MVME2304. Thank
119 * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and
120 * suggesting the appropriate code.
121 */
122
123enter_C_code:
124        bl      MMUon
125        bl      __eabi  /* setup EABI and SYSV environment */
126        bl      zero_bss
127        /*
128         * restore prep boot params
129         */
130        mr      r3,r31
131        mr      r4,r30
132        mr      r5,r29
133        mr      r6,r28
134        mr      r7,r27
135        bl      save_boot_params
136        /*
137         * stack = &__rtems_end + 4096
138         */
139        addis   r9,r0, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@ha
140        addi    r9,r9, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@l
141        /*
142         * align initial stack
143         * (we hope that the bootloader stack was 16-byte aligned
144         * or we haven't used altivec yet...)
145         */
146        li   r0, (CPU_STACK_ALIGNMENT-1)
147        andc r1, r9, r0
148        /*
149         * NULL ptr to back chain
150         */
151        li   r0, 0
152        stw  r0, 0(r1)
153
154        /*
155         * We are now in a environment that is totally independent from
156         * bootloader setup.
157         */
158    /* pass result of 'save_boot_params' to 'boot_card' in R3 */
159        bl      boot_card
160        bl      _return_to_ppcbug
161
162        .globl  MMUon
163        .type   MMUon,@function
164MMUon:
165        mfmsr   r0
166        ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
167#if (PPC_HAS_FPU == 0)
168        xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
169#else
170        xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
171#endif
172        mflr    r11
173        mtsrr0  r11
174        mtsrr1  r0
175        SYNC
176        rfi
177
178        .globl  MMUoff
179        .type   MMUoff,@function
180MMUoff:
181        mfmsr   r0
182        ori     r0,r0,MSR_IR| MSR_DR | MSR_IP
183        mflr    r11
184        xori    r0,r0,MSR_IR|MSR_DR
185        mtsrr0  r11
186        mtsrr1  r0
187        SYNC
188        rfi
189
190        .globl  _return_to_ppcbug
191        .type   _return_to_ppcbug,@function
192
193_return_to_ppcbug:
194        mflr    r30
195        bl      MMUoff
196        MONITOR_ENTER
197        bl      MMUon
198        mtctr   r30
199        bctr
200
201flush_tlbs:
202        lis     r20, 0x1000
2031:      addic.  r20, r20, -0x1000
204        tlbie   r20
205        bgt     1b
206        sync
207        blr
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