source: rtems/c/src/lib/libbsp/powerpc/mvme5500/start/start.S @ 169480b

4.115
Last change on this file since 169480b was 169480b, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 17, 2011 at 1:24:47 PM

2011-04-10 Kate Feng <feng@…>

PR 1786/bsps

  • Makefile.am: Add support for Altivec.
  • startup/bspstart.c, Makefile.am: Use shared/startup/zerobss.c instead.
  • make/custom/mvme5500.cfg: Change CPU_CFLAGS to "-mcpu=7450 -mtune=7450 -Dmpc7455"
  • irq/BSP_irq.c, pci/detect_host_bridge.c, pci.c, pcifinddevice.c: Remove warnings.
  • vme/VMEConfig.h, include/bsp.h: use VME shared IRQ handlers.
  • network/if_100MHz/GT64260eth.c: Recycle the Rx mbuf if there is any Rx error.
  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 *  start.S :     RTEMS entry point
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  S. Kate Feng <feng1@bnl.gov>, April 2004
7 *  Mapped the 2nd 256MB of RAM to support the MVME5500/MVME6100 boards
8 *     
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13<<<<<<< start.S
14 *  $Id$
15=======
16 *  $Id$
17>>>>>>> 1.25
18 *
19 */
20
21#include <rtems/asm.h>
22#include <rtems/score/cpu.h>
23#include <rtems/powerpc/powerpc.h>
24
25#include <libcpu/io.h>
26#include <libcpu/bat.h>
27#include <bspopts.h>
28
29#define SYNC \
30        sync; \
31        isync
32
33#define KERNELBASE      0x0
34#define MEM256MB        0x10000000
35
36#define MONITOR_ENTER                   \
37        mfmsr   r10             ;       \
38        ori     r10,r10,MSR_IP  ;       \
39        mtmsr   r10             ;       \
40        li      r10,0x63        ;       \
41        sc
42
43        .text
44        .globl  __rtems_entry_point
45        .type   __rtems_entry_point,@function
46__rtems_entry_point:
47#ifdef DEBUG_EARLY_START
48        MONITOR_ENTER
49#endif
50
51/*
52 * PREP
53 * This is jumped to on prep systems right after the kernel is relocated
54 * to its proper place in memory by the boot loader.  The expected layout
55 * of the regs is:
56 *   r3: ptr to residual data
57 *   r4: initrd_start or if no initrd then 0
58 *   r5: initrd_end - unused if r4 is 0
59 *   r6: Start of command line string
60 *   r7: End of command line string
61 *
62 *   The Prep boot loader insure that the MMU is currently off...
63 *
64 */
65
66        mr      r31,r3                  /* save parameters */
67        mr      r30,r4
68        mr      r29,r5
69        mr      r28,r6
70        mr      r27,r7
71
72#ifdef __ALTIVEC__
73        /* enable altivec; gcc may use it! */
74        mfmsr r0
75        oris  r0, r0, (1<<(31-16-6))
76        mtmsr r0
77        /*
78         * set vscr and vrsave to known values
79         */
80        li    r0, 0
81        mtvrsave r0
82        vxor   0,0,0
83        mtvscr 0
84#endif
85
86        /*
87         * Make sure we have nothing in BATS and TLB
88         */
89        bl      CPU_clear_bats_early
90        bl      flush_tlbs
91/*
92 * Use the first pair of BAT registers to map the 1st 256MB
93 * of RAM to KERNELBASE.
94 */
95        lis     r11,KERNELBASE@h
96/* set up BAT registers for 604 */
97        ori     r11,r11,0x1ffe
98        li      r8,2                    /* R/W access */
99        isync
100        mtspr   DBAT0L,r8               /* N.B. 6xx (not 601) have valid */
101        mtspr   DBAT0U,r11              /* bit in upper BAT register */
102        mtspr   IBAT0L,r8
103        mtspr   IBAT0U,r11
104        isync
105/*
106 * <skf> Use the 2nd pair of BAT registers to map the 2nd 256MB
107 * of RAM to 0x10000000.
108 */
109        lis     r11,MEM256MB@h
110        ori     r11,r11,0x1ffe          /* set up BAT1 registers for 604+ */
111        lis     r8,MEM256MB@h
112        ori     r8,r8,2
113        isync
114        mtspr   DBAT1L,r8               /* N.B. 6xx (not 601) have valid */
115        mtspr   DBAT1U,r11              /* bit in upper BAT register */
116        mtspr   IBAT1L,r8
117        mtspr   IBAT1U,r11
118        isync
119
120/*
121 * we now have the two 256M of ram mapped with the bats. We are still
122 * running on the bootloader stack and cannot switch to an RTEMS allocated
123 * init stack before copying the residual data that may have been set just
124 * after rtems_end address. This bug has been experienced on MVME2304. Thank
125 * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and
126 * suggesting the appropriate code.
127 */
128
129enter_C_code:
130        bl      MMUon
131        bl      __eabi  /* setup EABI and SYSV environment */
132        bl      zero_bss
133        /*
134         * restore prep boot params
135         */
136        mr      r3,r31
137        mr      r4,r30
138        mr      r5,r29
139        mr      r6,r28
140        mr      r7,r27
141        bl      save_boot_params
142        /*
143         * stack = &__rtems_end + 4096
144         */
145        addis   r9,r0, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@ha
146        addi    r9,r9, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@l
147        /*
148         * align initial stack
149         * (we hope that the bootloader stack was 16-byte aligned
150         * or we haven't used altivec yet...)
151         */
152        li   r0, (CPU_STACK_ALIGNMENT-1)
153        andc r1, r9, r0
154        /*
155         * We are now in a environment that is totally independent from
156         * bootloader setup.
157         */
158    /* pass result of 'save_boot_params' to 'boot_card' in R3 */
159        bl      boot_card
160        bl      _return_to_ppcbug
161
162        .globl  MMUon
163        .type   MMUon,@function
164MMUon:
165        mfmsr   r0
166        ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
167#if (PPC_HAS_FPU == 0)
168        xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
169#else
170        xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
171#endif
172        mflr    r11
173        mtsrr0  r11
174        mtsrr1  r0
175        SYNC
176        rfi
177
178        .globl  MMUoff
179        .type   MMUoff,@function
180MMUoff:
181        mfmsr   r0
182        ori     r0,r0,MSR_IR| MSR_DR | MSR_IP
183        mflr    r11
184        xori    r0,r0,MSR_IR|MSR_DR
185        mtsrr0  r11
186        mtsrr1  r0
187        SYNC
188        rfi
189
190        .globl  _return_to_ppcbug
191        .type   _return_to_ppcbug,@function
192
193_return_to_ppcbug:
194        mflr    r30
195        bl      MMUoff
196        MONITOR_ENTER
197        bl      MMUon
198        mtctr   r30
199        bctr
200
201flush_tlbs:
202        lis     r20, 0x1000
2031:      addic.  r20, r20, -0x1000
204        tlbie   r20
205        bgt     1b
206        sync
207        blr
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