[7be6ad9] | 1 | /* |
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| 2 | * start.S : RTEMS entry point |
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| 3 | * |
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| 4 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 5 | * |
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| 6 | * S. Kate Feng <feng1@bnl.gov>, April 2004 |
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| 7 | * Mapped the 2nd 256MB of RAM to support the MVME5500 boards. |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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| 11 | * http://www.rtems.com/license/LICENSE. |
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| 12 | * |
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| 13 | * |
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| 14 | */ |
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| 15 | |
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[1768b06] | 16 | #include <rtems/asm.h> |
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[7be6ad9] | 17 | #include <rtems/score/cpu.h> |
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| 18 | #include <libcpu/io.h> |
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| 19 | |
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| 20 | #define SYNC \ |
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| 21 | sync; \ |
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| 22 | isync |
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| 23 | |
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| 24 | #define KERNELBASE 0x0 |
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| 25 | #define MEM256MB 0x10000000 |
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| 26 | |
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| 27 | #define MONITOR_ENTER \ |
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| 28 | mfmsr r10 ; \ |
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| 29 | ori r10,r10,MSR_IP ; \ |
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| 30 | mtmsr r10 ; \ |
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| 31 | li r10,0x63 ; \ |
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| 32 | sc |
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| 33 | |
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| 34 | |
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| 35 | .text |
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| 36 | .globl __rtems_entry_point |
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| 37 | .type __rtems_entry_point,@function |
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| 38 | __rtems_entry_point: |
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| 39 | #ifdef DEBUG_EARLY_START |
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| 40 | MONITOR_ENTER |
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| 41 | #endif |
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| 42 | |
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| 43 | /* |
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| 44 | * PREP |
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| 45 | * This is jumped to on prep systems right after the kernel is relocated |
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| 46 | * to its proper place in memory by the boot loader. The expected layout |
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| 47 | * of the regs is: |
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| 48 | * r3: ptr to residual data |
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| 49 | * r4: initrd_start or if no initrd then 0 |
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| 50 | * r5: initrd_end - unused if r4 is 0 |
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| 51 | * r6: Start of command line string |
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| 52 | * r7: End of command line string |
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| 53 | * |
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| 54 | * The Prep boot loader insure that the MMU is currently off... |
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| 55 | * |
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| 56 | */ |
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| 57 | |
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| 58 | mr r31,r3 /* save parameters */ |
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| 59 | mr r30,r4 |
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| 60 | mr r29,r5 |
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| 61 | mr r28,r6 |
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| 62 | mr r27,r7 |
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| 63 | /* |
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| 64 | * Make sure we have nothing in BATS and TLB |
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| 65 | */ |
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| 66 | bl clear_bats |
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| 67 | bl flush_tlbs |
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| 68 | /* |
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| 69 | * Use the first pair of BAT registers to map the 1st 256MB |
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| 70 | * of RAM to KERNELBASE. |
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| 71 | */ |
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| 72 | lis r11,KERNELBASE@h |
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| 73 | ori r11,r11,0x1ffe /* set up BAT0 registers for 604+ */ |
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| 74 | li r8,2 /* R/W access */ |
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| 75 | isync |
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| 76 | mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ |
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| 77 | mtspr DBAT0U,r11 /* bit in upper BAT register */ |
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| 78 | mtspr IBAT0L,r8 |
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| 79 | mtspr IBAT0U,r11 |
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| 80 | isync |
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| 81 | /* |
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| 82 | * Use the 2nd pair of BAT registers to map the 2nd 256MB |
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| 83 | * of RAM to 0x10000000. <SKF> |
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| 84 | */ |
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| 85 | lis r11,MEM256MB@h |
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| 86 | ori r11,r11,0x1ffe /* set up BAT1 registers for 604+ */ |
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| 87 | lis r8,MEM256MB@h |
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| 88 | ori r8,r8,2 |
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| 89 | isync |
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| 90 | mtspr DBAT1L,r8 /* N.B. 6xx (not 601) have valid */ |
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| 91 | mtspr DBAT1U,r11 /* bit in upper BAT register */ |
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| 92 | mtspr IBAT1L,r8 |
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| 93 | mtspr IBAT1U,r11 |
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| 94 | isync |
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| 95 | |
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| 96 | /* |
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| 97 | * we now have the two 256M of ram mapped with the bats. We are still |
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| 98 | * running on the bootloader stack and cannot switch to an RTEMS allocated |
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| 99 | * init stack before copying the residual data that may have been set just |
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| 100 | * after rtems_end address. This bug has been experienced on MVME2304. Thank |
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| 101 | * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and |
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| 102 | * suggesting the appropriate code. |
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| 103 | */ |
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| 104 | |
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| 105 | enter_C_code: |
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| 106 | bl MMUon |
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| 107 | bl __eabi /* setup EABI and SYSV environment */ |
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| 108 | bl zero_bss |
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| 109 | /* |
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| 110 | * restore prep boot params |
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| 111 | */ |
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| 112 | mr r3,r31 |
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| 113 | mr r4,r30 |
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| 114 | mr r5,r29 |
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| 115 | mr r6,r28 |
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| 116 | mr r7,r27 |
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| 117 | bl save_boot_params |
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| 118 | /* |
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| 119 | * stack = &__rtems_end + 4096 |
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| 120 | */ |
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| 121 | addis r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha |
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| 122 | addi r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l |
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| 123 | mr r1, r9 |
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| 124 | /* |
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| 125 | * We are know in a environment that is totally independent from bootloader setup. |
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| 126 | */ |
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| 127 | lis r5,environ@ha |
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| 128 | la r5,environ@l(r5) /* environp */ |
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| 129 | li r4, 0 /* argv */ |
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| 130 | li r3, 0 /* argc */ |
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| 131 | bl boot_card |
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| 132 | bl _return_to_ppcbug |
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| 133 | |
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| 134 | .globl MMUon |
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| 135 | .type MMUon,@function |
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| 136 | MMUon: |
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| 137 | mfmsr r0 |
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| 138 | #if (PPC_HAS_FPU == 0) |
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| 139 | ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP |
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| 140 | xori r0, r0, MSR_EE | MSR_IP | MSR_FP |
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| 141 | #else |
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| 142 | ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP |
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| 143 | xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1 |
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| 144 | #endif |
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| 145 | mflr r11 |
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| 146 | mtsrr0 r11 |
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| 147 | mtsrr1 r0 |
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| 148 | SYNC |
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| 149 | rfi |
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| 150 | |
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| 151 | .globl MMUoff |
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| 152 | .type MMUoff,@function |
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| 153 | MMUoff: |
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| 154 | mfmsr r0 |
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| 155 | ori r0,r0,MSR_IR| MSR_DR | MSR_IP |
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| 156 | mflr r11 |
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| 157 | xori r0,r0,MSR_IR|MSR_DR |
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| 158 | mtsrr0 r11 |
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| 159 | mtsrr1 r0 |
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| 160 | SYNC |
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| 161 | rfi |
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| 162 | |
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| 163 | .globl _return_to_ppcbug |
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| 164 | .type _return_to_ppcbug,@function |
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| 165 | |
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| 166 | |
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| 167 | _return_to_ppcbug: |
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| 168 | mflr r30 |
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| 169 | bl MMUoff |
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| 170 | MONITOR_ENTER |
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| 171 | bl MMUon |
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| 172 | mtctr r30 |
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| 173 | bctr |
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| 174 | |
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| 175 | /* |
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| 176 | * An undocumented "feature" of 604e requires that the v bit |
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| 177 | * be cleared before changing BAT values. |
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| 178 | * |
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| 179 | * Also, newer IBM firmware does not clear bat3 and 4 so |
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| 180 | * this makes sure it's done. |
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| 181 | * -- Cort |
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| 182 | */ |
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| 183 | clear_bats: |
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| 184 | li r20,0 |
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| 185 | mfspr r9,PVR |
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| 186 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ |
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| 187 | cmpwi r9, 1 |
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| 188 | SYNC |
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| 189 | beq 1f |
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| 190 | mtspr DBAT0U,r20 |
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| 191 | mtspr DBAT0L,r20 |
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| 192 | mtspr DBAT1U,r20 |
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| 193 | mtspr DBAT1L,r20 |
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| 194 | mtspr DBAT2U,r20 |
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| 195 | mtspr DBAT2L,r20 |
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| 196 | mtspr DBAT3U,r20 |
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| 197 | mtspr DBAT3L,r20 |
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| 198 | 1: |
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| 199 | mtspr IBAT0U,r20 |
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| 200 | mtspr IBAT0L,r20 |
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| 201 | mtspr IBAT1U,r20 |
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| 202 | mtspr IBAT1L,r20 |
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| 203 | mtspr IBAT2U,r20 |
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| 204 | mtspr IBAT2L,r20 |
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| 205 | mtspr IBAT3U,r20 |
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| 206 | mtspr IBAT3L,r20 |
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| 207 | SYNC |
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| 208 | blr |
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| 209 | |
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| 210 | flush_tlbs: |
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| 211 | lis r20, 0x1000 |
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| 212 | 1: addic. r20, r20, -0x1000 |
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| 213 | tlbie r20 |
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| 214 | bgt 1b |
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| 215 | sync |
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| 216 | blr |
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| 217 | |
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| 218 | |
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| 219 | .comm environ,4,4 |
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